AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 347
AT91CAP7E-NA-ZJ
Manufacturer Part Number
AT91CAP7E-NA-ZJ
Description
MCU CAP7 FPGA 225LFBGA
Manufacturer
Atmel
Series
CAP™r
Specifications of AT91CAP7E-NA-ZJ
Core Processor
ARM7
Core Size
16/32-Bit
Speed
80MHz
Connectivity
EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
ROM
Ram Size
160K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
225-LFBGA
Processor Series
AT91Mx
Core
ARM7TDMI
Data Bus Width
32 bit
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
Quantity
Price
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29.6
29.6.1
8549A–CAP–10/08
Functional Description
Baud Rate Generator
The USART is capable of managing several types of serial synchronous or asynchronous
communications.
It supports the following communication modes:
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the
receiver and the transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode
Register (US_MR) between:
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field
of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate
Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and
becomes inactive.
• 5- to 9-bit full-duplex asynchronous serial communication
• High-speed 5- to 9-bit full-duplex synchronous serial communication
• RS485 with driver control signal
• ISO7816, T0 or T1 protocols for interfacing with smart cards
• InfraRed IrDA Modulation and Demodulation
• Test modes
• the Master Clock MCK
• a division of the Master Clock, the divider being product dependent, but generally set to 8
• the external clock, available on the SCK pin
– MSB- or LSB-first
– 1, 1.5 or 2 stop bits
– Parity even, odd, marked, space or none
– By 8 or by 16 over-sampling receiver frequency
– Optional hardware handshaking
– Optional modem signals management
– Optional break management
– Optional multidrop serial communication
– MSB- or LSB-first
– 1 or 2 stop bits
– Parity even, odd, marked, space or none
– By 8 or by 16 over-sampling frequency
– Optional hardware handshaking
– Optional modem signals management
– Optional break management
– Optional multidrop serial communication
– NACK handling, error counter with repetition and iteration limit
– Remote loopback, local loopback, automatic echo
AT91CAP7E
347
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