AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 495
AT91CAP7E-NA-ZJ
Manufacturer Part Number
AT91CAP7E-NA-ZJ
Description
MCU CAP7 FPGA 225LFBGA
Manufacturer
Atmel
Series
CAP™r
Specifications of AT91CAP7E-NA-ZJ
Core Processor
ARM7
Core Size
16/32-Bit
Speed
80MHz
Connectivity
EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
ROM
Ram Size
160K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
225-LFBGA
Processor Series
AT91Mx
Core
ARM7TDMI
Data Bus Width
32 bit
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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33.10.5
The SDRAM Controller satisfies the timing of standard SDRAM modules given in
corners.
Timings are given assuming a capacitance load on data, control and address pads :
Table 33-26. Capacitance Load on Data, Control and Address Pads
Table 33-27. Capacitance Load on SDCK Pad
Table 33-28. SDRAMC Timings
Control/Address is the set of following timings : A0-A9, A11-A13, SDA10, SDCKE, SDCS, RAS, CAS, BAx, DQMx, and
SDWE
8549A–CAP–10/08
Supply
3.3V
1.8V
Supply
3.3V
1.8V
Symbol
SDRAMC
SDRAMC
SDRAMC
SDRAMC
1
2
3
4
SDRAMC Timings
Parameter
Control/Address/Data out valid before SDCK Rising Edge
Control/Address/Data out change after SDCK Rising Edge
Data Input Setup before SDCK Rising Edge
Data Input Hold after SDCK Rising Edge
MAX
50pF
30 pF
MAX
10pF
10pF
STH
50pF
30 pF
STH
10pF
10pF
Corner
Corner
(1)
(1)
MIN
0 pF
0 pF
MIN
10pF
10pF
0.5*t
0.5*t
3.3V Supply
CPMCK+
CPMCK+
TBD
TBD
Min
Table 33-28
TBD
TBD
Units
ns
ns
ns
ns
AT91CAP7E
and in MAX and STH
495
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