ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 120
ATSAM3S4CA-AU
Manufacturer Part Number
ATSAM3S4CA-AU
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4CA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
79
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 16x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
79
Ram Memory Size
48KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Cpu Family
AT91
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
64MHz
Total Internal Ram Size
48KB
# I/os (max)
79
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.62V
On-chip Adc
16-chx12-bit
On-chip Dac
2-chx12-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4CA-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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10.14.1
10.14.1.1
10.14.1.2
10.14.1.3
10.14.1.4
10.14.1.5
120
MUL
MLA
MULS
MULLT
MLS
SAM3S Preliminary
MUL, MLA, and MLS
Syntax
Operation
Restrictions
Condition flags
Examples
R10, R2, R5
R10, R2, R1, R5 ; Multiply with accumulate, R10 = (R2 x R1) + R5
R0, R2, R2
R2, R3, R2
R4, R5, R6, R7
Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and pro-
ducing a 32-bit result.
where:
cond
S
result of the operation, see
Rd
Rn, Rm
Ra
The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32
bits of the result in Rd.
The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places
the least significant 32 bits of the result in Rd.
The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the value
from Ra, and places the least significant 32 bits of the result in Rd.
The results of these instructions do not depend on whether the operands are signed or
unsigned.
In these instructions, do not use SP and do not use PC.
If you use the S suffix with the MUL instruction:
If S is specified, the MUL instruction:
• Rd, Rn, and Rm must all be in the range R0 to R7
• Rd must be the same as Rm
• you must not use the cond suffix.
• updates the N and Z flags according to the result
• does not affect the C and V flags.
MUL{S}{cond} {Rd,} Rn, Rm ; Multiply
MLA{cond} Rd, Rn, Rm, Ra
MLS{cond} Rd, Rn, Rm, Ra
; Multiply, R10 = R2 x R5
; Multiply with flag update, R0 = R2 x R2
; Conditionally multiply, R2 = R3 x R2
; Multiply with subtract, R4 = R7 - (R5 x R6)
is an optional condition code, see
is an optional suffix. If S is specified, the condition code flags are updated on the
is the destination register. If Rd is omitted, the destination register is Rn.
are registers holding the values to be multiplied.
is a register holding the value to be added or subtracted from.
“Conditional execution” on page
; Multiply with accumulate
; Multiply with subtract
“Conditional execution” on page
84.
6500C–ATARM–8-Feb-11
84.
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