ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 942
ATSAM3S4CA-CU
Manufacturer Part Number
ATSAM3S4CA-CU
Description
IC MCU 32BIT 256KB FLASH 100BGA
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4CA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
79
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 16x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Package
100LFBGA
Device Core
ARM Cortex M3
Family Name
AT91
Maximum Speed
64 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
79
Interface Type
I2C/I2S/SPI/UART/USART/USB
On-chip Adc
16-chx12-bit
On-chip Dac
2-chx12-bit
Number Of Timers
6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S4CA-CU
Manufacturer:
SANYO
Quantity:
1 000
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37.6.3.6
37.6.3.7
37.6.3.8
942
SAM3S Preliminary
Entering in Suspend State
Receiving a Host Resume
Sending a Device Remote Wakeup
When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the
UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR
register.This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend
Mode.
In this state bus powered devices must drain less than 500uA from the 5V VBUS. As an exam-
ple, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes
into Idle Mode. It may also switch off other devices on the board.
The USB device peripheral clocks can be switched off. Resume event is asynchronously
detected. MCK and UDPCK can be switched off in the Power Management controller and the
USB transceiver can be disabled by setting the TXVDIS field in the UDP_TXVC register.
Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the
UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations
after writing to the UDP_TXVC and acknowledging the RXSUSP.
In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver
and clocks are disabled (however the pull-up shall not be removed).
Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may gen-
erate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be
used to wake up the core, enable PLL and main oscillators and configure clocks.
Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the
UDP peripheral. MCK for the UDP must be enabled before clearing the WAKEUP bit in the
UDP_ICR register and clearing TXVDIS in the UDP_TXVC register.
In Suspend state it is possible to wake up the host sending an external resume.
Before sending a K state to the host, MCK, UDPCK and the transceiver must be enabled. Then
to enable the remote wakeup feature, the RMWUPE bit in the UDP_GLB_STAT register must be
enabled. To force the K state on the line, a transition of the ESR bit from 0 to 1 has to be done in
the UDP_GLB_STAT register. This transition must be accomplished by first writing a 0 in the
ESR bit and then writing a 1.
The K state is automatically generated and released according to the USB 2.0 specification.
• The device must wait at least 5 ms after being entered in suspend before sending an external
• The device has 10 ms from the moment it starts to drain current and it forces a K state to
• The device must force a K state from 1 to 15 ms to resume the host
resume.
resume the host.
6500C–ATARM–8-Feb-11
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