ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 285
![MCU AVR 256KB FLASH A3B 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATXMEGA256A3B-MH
Manufacturer Part Number
ATXMEGA256A3B-MH
Description
MCU AVR 256KB FLASH A3B 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA256A3B-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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24.12.2
8077H–AVR–12/09
CTRLB (SRAM) - Chip Select Control Register B
Table 24-17. Address space encoding (Continued)
1.
• Bit 1:0 - MODE[1:0]: Chip Select Mode
These bits select the Chip Select Mode and decide what type of interface is used for the external
memory or peripheral according to
Table 24-18. Chip Select Mode selection
1.
This configuration options in this register depend on the Chip Select Mode configuration. The
register description below is valid when the Chip Select Mode is configured for SRAM or SRAM
LPC.
• Bit 7:3 - Reserved
These bits are reserved and will always be read as zero.
• Bit 2:0 - SRWS[2:0]: SRAM Wait State
These bits select the number of wait states for SRAM and SRAM LPC access as a number of
Peripheral 2x clock (CLK
Table 24-19. Wait State selection
Bit
+0x01
Read/Write
Initial Value
ASIZE[5:0]
01111
10000
Other
MODE[1:0]
SRWS[2:0]
Entire available data space used.
SDRAM can only be selected for CS3
000
001
010
011
100
00
01
10
11
R/W
7
0
-
R/W
6
0
-
Group Configuration
8M
16M
Group Configuration
DISABLE
SRAM
LPC
SDRAM
Group Configuration
0CLK
1CLK
2CLK
3CLK
4CLK
PER2
) cycles, according to
R/W
5
0
-
Table 24-18 on page
R/W
4
0
-
Address Size
8M Bytes
16M
-
Description
Chip Select Disabled
Enable Chip Select for SRAM
Enable Chip Select for SRAM LPC
Enable Chip Select for SDRAM
Description
0 CLK
1 CLK
2 CLK
3 CLK
4 CLK
R/W
3
0
-
Table 24-19 on page
(1)
PER2
PER2
PER2
PER2
PER2
285.
cycles wait state
cycles wait state
cycles wait state
cycles wait state
cycles wait state
R/W
2
0
Address Lines Compared
ADDR[23]
-
Reserved
SRWS[2:0]
R/W
1
0
285.
R/W
(1)
0
0
XMEGA A
CTRLB
285
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