ATSAM3U2EA-CU Atmel, ATSAM3U2EA-CU Datasheet - Page 180
ATSAM3U2EA-CU
Manufacturer Part Number
ATSAM3U2EA-CU
Description
IC MCU 32BIT 128KB FLSH 144LFBGA
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2EA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b, 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
4xUSART, 2xTWI, 5xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
96
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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13.20 System control block
Table 13-30. Summary of the system control block registers
Notes:
13.20.1
180
Address
0xE000E008
0xE000ED00
0xE000ED04
0xE000ED08
0xE000ED0C
0xE000ED10
0xE000ED14
0xE000ED18
0xE000ED1C
0xE000ED20
0xE000ED24
0xE000ED28
0xE000ED28
0xE000ED29
0xE000ED2A
0xE000ED2C
0xE000ED34
0xE000ED38
0xE000ED3C
1. See the register description for more information.
2. A subregister of the CFSR.
SAM3U Series
The CMSIS mapping of the Cortex-M3 SCB registers
Name
ACTLR
CPUID
ICSR
VTOR
AIRCR
SCR
CCR
SHPR1
SHPR2
SHPR3
SHCRS
CFSR
MMSR
BFSR
UFSR
HFSR
MMAR
BFAR
AFSR
(2)
(2)
(2)
The System control block (SCB) provides system implementation information, and system con-
trol. This includes configuration, control, and reporting of the system exceptions. The system
control block registers are:
To improve software efficiency, the CMSIS simplifies the SCB register presentation. In the
CMSIS, the byte array SHP[0] to SHP[12] corresponds to the registers SHPR1-SHPR3.
Type
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
(1)
(1)
Required
privilege
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Reset
value
0x00000000
0x412FC230
0x00000000
0x00000000
0xFA050000
0x00000000
0x00000200
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00
0x00
0x0000
0x00000000
Unknown
0x00000000
Unknown
Description
“Auxiliary Control Register” on page 181
“CPUID Base Register” on page 182
“Interrupt Control and State Register” on page 183
“Vector Table Offset Register” on page 186
“Application Interrupt and Reset Control Register” on page
187
“System Control Register” on page 189
“Configuration and Control Register” on page 190
“System Handler Priority Register 1” on page 193
“System Handler Priority Register 2” on page 194
“System Handler Priority Register 3” on page 194
“System Handler Control and State Register” on page 195
“Configurable Fault Status Register” on page 197
“Memory Management Fault Address Register” on page
204
“Bus Fault Status Register” on page 199
“Usage Fault Status Register” on page 201
“Hard Fault Status Register” on page 203
“Memory Management Fault Address Register” on page
204
“Bus Fault Address Register” on page 205
“Auxiliary Fault Status Register” on page 206
6430D–ATARM–25-Mar-11
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