ATSAM3U2EA-CU Atmel, ATSAM3U2EA-CU Datasheet - Page 513

• Manufacturer Part Number: ATSAM3U2EA-CU
• Description: IC MCU 32BIT 128KB FLSH 144LFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U2EA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b, 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 36 KB
• Interface Type: 4xUSART, 2xTWI, 5xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 30-8. Input Change Interrupt Timings if there are no Additional Interrupt Modes
30.5.11
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Read PIO_ISR
Pin Level
PIO_ISR
MCK
I/O Lines Lock
The other lines are configured in Falling Edge or Low Level detection by default, if they have not
been previously configured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low
Level detection by writing 32’h0000_004A in PIO_FELLSR.
When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller
PWM), it can become locked by the action of this peripheral via an input of the PIO controller.
When an I/O line is locked, the write of the corresponding bit in the registers PIO_PER,
PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER and PIO_ABSR is discarded in
order to lock its configuration. The user can know at anytime which I/O line is locked by reading
the PIO Lock Status register PIO_LOCKSR. Once an I/O line is locked, the only way to unlock it
is to apply an hardware reset to the PIO Controller.
APB Access
SAM3U Series
SAM3U Series
APB Access
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