P89LPC9151FDH,129 NXP Semiconductors, P89LPC9151FDH,129 Datasheet
P89LPC9151FDH,129
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P89LPC9151/9161/9171 8-bit microcontroller with accelerated two-clock 80C51 core byte-erasable flash with 8-bit ADC Rev. 02 — 9 February 2010 1. General description The P89LPC9151/9161/9171 is a single-chip microcontroller, available in low cost packages, based on a ...
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... NXP Semiconductors 2.2 Additional features A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI ...
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... NXP Semiconductors 3. Ordering information Table 1. Type number P89LPC9151FDH P89LPC9161FDH P89LPC9171FDH 3.1 Ordering options Table 2. Type number P89LPC9151FDH P89LPC9161FDH P89LPC9171FDH P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 Ordering information Package Name Description TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm TSSOP16 plastic thin shrink small outline package ...
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... NXP Semiconductors 4. Block diagram P89LPC9151 2 kB CODE FLASH 256 BYTE DATA RAM P1[5:0] CONFIGURABLE I/O P0[5:0] CONFIGURABLE I/O KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER external clock input OSCILLATOR Fig 1. Block diagram (P89LPC9151) P89LPC9151_61_71_2 Product data sheet HIGH PERFORMANCE ...
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... NXP Semiconductors P89LPC9161 2 kB CODE FLASH 256 BYTE DATA RAM P2[5:2] CONFIGURABLE I/O P1.5, P1[3:0] CONFIGURABLE I/O P0[5:1] CONFIGURABLE I/O KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER external clock input OSCILLATOR Fig 2. Block diagram (P89LPC9161) P89LPC9151_61_71_2 Product data sheet ...
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... NXP Semiconductors P89LPC9171 2 kB CODE FLASH 256 BYTE DATA RAM P2.2 CONFIGURABLE I/O P1[5:0] CONFIGURABLE I/O P0.7, P[5:0] CONFIGURABLE I/O KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER external clock input OSCILLATOR clkout Fig 3. Block diagram (P89LPC9171) P89LPC9151_61_71_2 Product data sheet ...
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... NXP Semiconductors 5. Functional diagram KBI0 AD10 KBI1 AD11 KBI2 AD12 KBI3 AD13 DAC1 KBI4 CLKIN KBI5 Fig 4. Functional diagram (P89LPC9151) KBI1 AD10 KBI2 AD11 AD12 KBI3 AD13 DAC1 KBI4 CLKIN KBI5 Fig 5. Functional diagram (P89LPC9161) P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 V DD ...
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... NXP Semiconductors KBI0 AD10 KBI1 AD11 KBI2 AD12 KBI3 AD13 DAC1 KBI4 CLKIN KBI5 CLKOUT KBI7 Fig 6. Functional diagram (P89LPC9171) P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 V DD CMP2 CIN2B CIN2A CIN1B PORT 0 P89LPC9171 CIN1A CMPREF T1 Rev. 02 — 9 February 2010 8-bit microcontroller with 8-bit ADC ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 7. Fig 8. Fig 9. P89LPC9151_61_71_2 Product data sheet P0.1/CIN2B/KBI1/AD10 1 2 P0.0/CMP2/KBI0 3 P1.5/RST P89LPC9151 P1.4/INT1 5 P1.3/INT0/SDA 6 7 P1.2/T0/SCL P89LPC9151 TSSOP14 pin configuration 1 P0.1/CIN2B/KBI1/AD10 P2.4/SS 2 P1.5/RST P89LPC9161 5 P2.3/MISO 6 P2.2/MOSI P1.3/INT0/SDA 7 P1.2/T0/SCL 8 P89LPC9161 TSSOP16 pin configuration P0.1/CIN2B/KBI1/AD10 1 2 P0.0/CMP2/KBI0 3 P1 ...
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... NXP Semiconductors 6.2 Pin description Table 3. P89LPC9151 Pin description Symbol Pin TSSOP14 P0.0 to P0.5 P0.0/CMP2/ 2 KBI0 P0.1/CIN2B/ 1 KBI1/AD10 P0.2/CIN2A/ 14 KBI2/AD11 P0.3/CIN1B/ 13 KBI3/AD12 P0.4/CIN1A/ 12 KBI4/DAC1/AD13 P0.5/CMPREF/ 11 KBI5 P1.0 to P1.5 P89LPC9151_61_71_2 Product data sheet Type Description I/O Port 0: Port 6-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled ...
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... NXP Semiconductors Table 3. P89LPC9151 Pin description Symbol Pin TSSOP14 P1.0/TXD 9 P1.1/RXD 8 P1.2/T0/SCL 7 P1.3/INT0/SDA 6 P1.4/INT1 5 P1.5/RST [1] Input/output for P1.0 to P1.4. Input for P1.5. P89LPC9151_61_71_2 Product data sheet Type Description I/O P1.0 — Port 1 bit 0. O TXD — Transmitter output for serial port. ...
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... NXP Semiconductors Table 4. P89LPC9161 Pin description Symbol Pin TSSOP16 P0.1 to P0.5 P0.1/CIN2B/ 1 KBI1/AD10 P0.2/CIN2A/ 16 KBI2/AD11 P0.3/CIN1B/ 15 KBI3/AD12 P0.4/CIN1A/ 14 KBI4/DAC1/AD13 P0.5/CMPREF/ 13 KBI5 P1.0 to P1.3, P1.5 P1.0/TXD 10 P1.1/RXD 9 P89LPC9151_61_71_2 Product data sheet Type Description I/O Port 0: Port 5-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled ...
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... NXP Semiconductors Table 4. P89LPC9161 Pin description Symbol Pin TSSOP16 P1.2/T0/SCL 8 P1.3/INT0/SDA 7 P1.5/RST 3 P2.2 to P2.5 P2.2/MOSI 6 P2.3/MISO 5 P2.4/SS 2 P2.5/SPICLK [1] Input/output for P1.0 to P1.3. Input for P1.5. P89LPC9151_61_71_2 Product data sheet Type Description I/O P1.2 — Port 1 bit 2 (open-drain when used as output). I/O T0 — ...
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... NXP Semiconductors Table 5. P89LPC9171 Pin description Symbol Pin TSSOP16 P0.0 to P0.5, P0.7 P0.0/CMP2/ 2 KBI0 P0.1/CIN2B/ 1 KBI1/AD10 P0.2/CIN2A/ 16 KBI2/AD11 P0.3/CIN1B/ 15 KBI3/AD12 P0.4/CIN1A/ 14 KBI4/DAC1/AD13 P0.5/CMPREF/ 13 KBI5/CLKIN P0.7/T1/KBI7/CLK 11 OUT P89LPC9151_61_71_2 Product data sheet Type Description I/O Port 0: Port 6-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled ...
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... NXP Semiconductors Table 5. P89LPC9171 Pin description Symbol Pin TSSOP16 P1.0 to P1.5 P1.0/TXD 10 P1.1/RXD 9 P1.2/T0/SCL 8 P1.3/INT0/SDA 7 P1.4/INT1 6 P1.5/RST 3 P2 [1] Input/output for P1.0 to P1.4. Input for P1.5. P89LPC9151_61_71_2 Product data sheet Type Description I/O, I Port 1: Port 6-bit I/O port with a user-configurable output type, except for [1] three pins as noted below ...
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... NXP Semiconductors 7. Functional description Remark: Please refer to the P89LPC9151/9161/9171 User manual for a more detailed functional description. 7.1 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. ...
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Table 6. Special function registers - P89LPC9151 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 ACC* Accumulator E0H ADCON1 A/D control 97H ENBI1 register 1 ADINS A/D input A3H ...
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Table 6. Special function registers - P89LPC9151 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB [2] BRGR1 Baud rate BFH generator 0 rate high BRGCON Baud rate BDH - generator 0 control ...
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Table 6. Special function registers - P89LPC9151 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address DF 2 I2CON* I C-bus control D8H - register 2 I2DAT I C-bus data DAH ...
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Table 6. Special function registers - P89LPC9151 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB KBMASK Keypad 86H interrupt mask register KBPATN Keypad pattern 93H register Bit address 87 P0* Port 0 ...
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Table 6. Special function registers - P89LPC9151 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB RTCH RTC register D2H high RTCL RTC register D3H low SADDR Serial port A9H address register SADEN ...
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Table 6. Special function registers - P89LPC9151 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB WDCON Watchdog A7H PRE2 control register WDL Watchdog load C1H WFEED1 Watchdog C2H feed 1 WFEED2 Watchdog ...
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Table 7. Extended special function registers - P89LPC9151 Name Description SFR Bit functions and addresses addr. BODCFG BOD FFC8H configuration register CLKCON CLOCK Control FFDEH CLKOK register RTCDATH Real-time clock FFBFH data register high RTCDATL Real-time clock FFBEH data register ...
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Table 8. Special function registers - P89LPC9161 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 ACC* Accumulator E0H ADCON1 A/D control 97H ENBI1 register 1 ADINS A/D input A3H ...
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Table 8. Special function registers - P89LPC9161 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB [2] BRGR1 Baud rate BFH generator 0 rate high BRGCON Baud rate BDH - generator 0 control ...
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Table 8. Special function registers - P89LPC9161 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address DF 2 I2CON* I C-bus control D8H - register 2 I2DAT I C-bus data DAH ...
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Table 8. Special function registers - P89LPC9161 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB KBMASK Keypad 86H interrupt mask register KBPATN Keypad pattern 93H register Bit address 87 P0* Port 0 ...
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Table 8. Special function registers - P89LPC9161 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB PT0AD Port 0 digital F6H - input disable RSTSRC Reset source DFH - register RTCCON RTC control ...
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Table 8. Special function registers - P89LPC9161 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address 8F TCON* Timer 0 and 1 88H TF1 control TH0 Timer 0 high 8CH TH1 ...
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Table 9. Extended special function registers - P89LPC9161 Name Description SFR Bit functions and addresses addr. BODCFG BOD FFC8H configuration register CLKCON CLOCK Control FFDEH CLKOK register RTCDATH Real-time clock FFBFH data register high RTCDATL Real-time clock FFBEH data register ...
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Table 10. Special function registers - P89LPC9171 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 ACC* Accumulator E0H ADCON1 A/D control 97H ENBI1 register 1 ADINS A/D input A3H ...
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Table 10. Special function registers - P89LPC9171 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB [2] BRGR1 Baud rate BFH generator 0 rate high BRGCON Baud rate BDH - generator 0 control ...
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Table 10. Special function registers - P89LPC9171 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address DF 2 I2CON* I C-bus control D8H - register 2 I2DAT I C-bus data DAH ...
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Table 10. Special function registers - P89LPC9171 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB KBMASK Keypad 86H interrupt mask register KBPATN Keypad pattern 93H register Bit address 87 P0* Port 0 ...
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Table 10. Special function registers - P89LPC9171 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB PT0AD Port 0 digital F6H - input disable RSTSRC Reset source DFH - register RTCCON RTC control ...
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Table 10. Special function registers - P89LPC9171 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB TMOD Timer 0 and 1 89H T1GATE mode TRIM Internal 96H RCCLK oscillator trim register WDCON Watchdog ...
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Table 11. Extended special function registers - P89LPC9171 Name Description SFR Bit functions and addresses addr. BODCFG BOD FFC8H configuration register CLKCON CLOCK Control FFDEH CLKOK register RTCDATH Real-time clock FFBFH data register high RTCDATL Real-time clock FFBEH data register ...
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... NXP Semiconductors 7.2 Enhanced CPU The P89LPC9151/9161/9171 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 7.3 Clocks 7.3.1 Clock definitions The P89LPC9151/9161/9171 device has several internal clocks as defined below: OSCCLK — ...
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... NXP Semiconductors running at 8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until V has reached its specified level. 7.6 Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to ± ...
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... NXP Semiconductors 7.9 CCLK wake-up delay The P89LPC9151/9161/9171 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60 μ ...
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... NXP Semiconductors 7.12 Memory organization The various P89LPC9151/9161/9171 memory spaces are as follows: • DATA 128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. ...
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... NXP Semiconductors Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source ...
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... NXP Semiconductors RTCF ERTC (RTCCON.1) WDOVF (P89LPC9161) ENADCI1 ADCI1 ENBI1 BNDI1 Fig 11. Interrupt sources, interrupt enables, and power-down wake-up sources P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 IE0 EX0 IE1 EX1 BOIF EBO KBIF EKBI EWDRT CMF2 CMF1 EC EA (IE0.7) TF0 ET0 TF1 ...
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... NXP Semiconductors 7.15 I/O ports The P89LPC9151 has two I/O ports: Port 0 and Port 1. Ports 0 and 1 are both 6-bit ports. The P89LPC9161/9171 has three I/O ports: Port 0, Port 1 and Port 2. Ports 0 is 5-bit ports in the P89LPC9161 and 7-bit ports in the P89LPC9171, Port 1 is 5-bit ports in the P89LPC9161 and 6-bit ports in the P89LPC9171, Port 2 is 4-bit ports in the P89LPC9161 and 1-bit port in the P89LPC9171 ...
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... NXP Semiconductors LOW driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. The P89LPC9151/9161/9171 device, but the pins are 5 V tolerant. In ...
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... NXP Semiconductors Every output on the P89LPC9151/9161/9171 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals ...
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... NXP Semiconductors 7.17.2 Power-down mode The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC9151/9161/9171 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the data retention supply voltage V entered. SFR contents are not guaranteed after highly recommended to wake-up the processor via reset in this case ...
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... NXP Semiconductors • During a power-on reset, both POF and BOF are set but the other flag bits are cleared. • A Watchdog reset is similar to a power-on reset, both POF and BOF are set but the other flag bits are cleared. • For any other reset, previously set flag bits that have not been cleared will remain set. ...
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... NXP Semiconductors 7.19.6 Timer overflow toggle output Timer 0 (and Timer 1 on the P89LPC9171) can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on ...
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... NXP Semiconductors Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9 bit is not saved. The baud rate is programmable to either frequency, as determined by the SMOD1 bit in PCON. 7.21.4 Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9 the same as Mode 2 in all respects except baud rate ...
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... NXP Semiconductors Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0) ...
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... NXP Semiconductors P1.3/SDA P1.2/SCL Fig 14. I P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 P1.3 INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL status bus I2STAT 2 C-bus serial interface block diagram Rev. 02 — 9 February 2010 8-bit microcontroller with 8-bit ADC ...
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... NXP Semiconductors 7.23 SPI (P89LPC9161) The P89LPC9161 provides another high-speed serial communication interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode Mbit/s can be supported in either Master mode or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection ...
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... NXP Semiconductors 7.23.1 Typical SPI configurations Fig 16. SPI single master single slave configuration Fig 17. SPI dual device configuration, where either can be a master or a slave P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 master MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK PORT GENERATOR ...
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... NXP Semiconductors Fig 18. SPI single master multiple slaves configuration 7.24 Analog comparators Two analog comparators are provided on the P89LPC9151/9161/9171. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable inputs) is greater than the negative input (selectable from a pin or an internal reference voltage) ...
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... NXP Semiconductors (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF V ref(bg) (P0.2) CIN2A (P0.1) CIN2B Fig 19. Comparator input and output connections 7.24.1 Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred 1.23 V ± ...
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... NXP Semiconductors 7.25 KBI The Keypad Interrupt function (KBI) is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks ...
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... NXP Semiconductors MOV WFEED1, #0A5H MOV WFEED2, #05AH Watchdog oscillator ÷32 PCLK WDCON (A7H) (1) Watchdog reset can also be caused by an invalid feed sequence writing to WDCON not immediately followed by a feed sequence. Fig 20. Watchdog timer in Watchdog mode (WDTE = 1) 7.27 Additional features 7.27.1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely external reset or watchdog reset had occurred ...
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... NXP Semiconductors P89LPC9151/9161/9171 uses V algorithms. When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and flash erase/program is blocked. 7.28.2 Features • Programming and erase over the full operating voltage range. • Byte erase allows code memory to be used for data storage. ...
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... NXP Semiconductors board area. The ICP function uses five pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC9151/9161/9171 User manual. 7.28.7 IAP-Lite IAP-Lite is performed in the application under the control of the microcontroller’s firmware. ...
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... NXP Semiconductors Edge triggered. 8-bit conversion time of ≥ 1.61 μ A/D clock of 8.0 MHz. Interrupt or polled operation. Boundary limits interrupt. DAC output to a port pin with high output impedance. Clock divider. Power-down mode. 8.3 Block diagram Fig 21. ADC block diagram 8.4 ADC operating modes 8 ...
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... NXP Semiconductors all selected channels have been converted. The process will repeat starting with the first selected channel. Additional conversion results will again cycle through the four result register pairs, overwriting the previous results. Continuous conversions continue until terminated by the user. ...
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... NXP Semiconductors criteria, the boundary limits will again be compared after all 8 bits have been converted. The boundary status register (BNDSTA0) flags the channels which caused a boundary interrupt. 8.7 DAC output to a port pin with high output impedance The DAC block of ADC1 can be output to a port pin. In this mode, the AD1DAT3 register is used to hold the value fed to the DAC ...
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... NXP Semiconductors 9. Limiting values Table 15. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter T bias ambient temperature amb(bias) T storage temperature stg I HIGH-level output current per OH(I/O) input/output pin I LOW-level output current per OL(I/O) input/output pin I maximum total input/output current ...
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... NXP Semiconductors 10. Static characteristics Table 16. Static characteristics 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter I operating supply current DD(oper) I Idle mode supply current DD(idle) I Power-down mode supply DD(pd) current I total Power-down mode ...
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... NXP Semiconductors Table 16. Static characteristics 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter R internal pull-up resistance RST_N(int) on pin RST V band gap reference voltage ref(bg) TC band gap temperature bg coefficient [1] Typical ratings are not guaranteed. The values listed are at room temperature ...
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... NXP Semiconductors 10.1 Current characteristics Note: The graphs provided are a statistical summary based on a limited number of samples and only for information purposes. The performance characteristics listed are not tested or guaranteed. (mA) Fig 23. I (mA) Fig 24. I P89LPC9151_61_71_2 Product data sheet 2.4 2.8 Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock. versus frequency at +25 ° ...
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... NXP Semiconductors (mA) Fig 25. I (mA) Fig 26. I P89LPC9151_61_71_2 Product data sheet 2.4 2.8 Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock. versus frequency at +85 °C DD(oper) 5 4.0 3.0 2.0 1.0 0.0 2.4 2.8 Test conditions: idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. versus frequency at +25 ° ...
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... NXP Semiconductors (mA) Fig 27. I (mA) Fig 28. I P89LPC9151_61_71_2 Product data sheet 5 4.0 3.0 2.0 1.0 0.0 2.4 2.8 Test conditions: idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. ...
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... NXP Semiconductors (μA) (1) +85 °C (2) +25 °C (3) −40 °C Fig 29. I (μA) (1) +85 °C (2) −40 °C (3) +25 °C Fig 30. I P89LPC9151_61_71_2 Product data sheet 20 18.0 16.0 14.0 12.0 10.0 2.4 2.8 Test conditions: power-down mode, using internal RC oscillator with the following functions disabled: comparators, real-time clock, and watchdog timer ...
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... NXP Semiconductors 10.2 Internal RC/watchdog oscillator characteristics Note: The graphs provided are a statistical summary based on a limited number of samples and only for information purposes. The performance characteristics listed are not tested or guaranteed. frequency deviation (%) Fig 31. Average internal RC oscillator frequency versus V frequency ...
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... NXP Semiconductors frequency deviation (%) Fig 33. Average internal RC oscillator frequency versus V frequency deviation (%) Fig 34. Average watchdog oscillator frequency versus V P89LPC9151_61_71_2 Product data sheet 0.2 0 −0.2 −0.4 −0.6 2.4 2.8 Central frequency of internal RC oscillator = 7.3728 MHz 2.5 1.5 0.5 −0.5 −1.5 2.4 2.8 Central frequency of watchdog oscillator = 400 kHz Rev. 02 — ...
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... NXP Semiconductors frequency deviation (%) Fig 35. Average watchdog oscillator frequency versus V frequency deviation (%) Fig 36. Average watchdog oscillator frequency versus V P89LPC9151_61_71_2 Product data sheet 0.5 −0.5 −1.5 −2.5 −3.5 2.4 2.8 Central frequency of watchdog oscillator = 400 kHz 1.5 0.5 −0.5 −1.5 −2.5 2.4 2 ...
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... NXP Semiconductors 10.3 BOD characteristics Table 17. BOD static characteristics 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter BOD interrupt V trip voltage trip BOD reset V trip voltage trip BOD EEPROM/FLASH V trip voltage ...
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... NXP Semiconductors 11. Dynamic characteristics Table 18. Dynamic characteristics (12 MHz 2 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter f internal RC oscillator osc(RC) frequency f internal watchdog osc(WD) oscillator frequency f oscillator frequency osc T clock cycle time cy(clk) ...
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... NXP Semiconductors Table 18. Dynamic characteristics (12 MHz 2 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter T SPI cycle time SPICYC slave master t SPI enable lead time SPILEAD slave t SPI enable lag time SPILAG slave ...
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... NXP Semiconductors Table 19. Dynamic characteristics (18 MHz 3 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter f internal RC oscillator osc(RC) frequency f internal watchdog osc(WD) oscillator frequency f oscillator frequency osc T clock cycle time cy(clk) f low-power select clock ...
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... NXP Semiconductors Table 19. Dynamic characteristics (18 MHz 3 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter t SPI enable lead time SPILEAD slave t SPI enable lag time SPILAG slave t SPICLK HIGH time SPICLKH slave master ...
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... NXP Semiconductors 11.1 Waveforms Fig 38. External clock timing (with an amplitude of at least V clock t QVXH output data write to SBUF t XHDV input data clear RI Fig 39. Shift register mode timing SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t MOSI SPIF (output) Fig 40. SPI master timing (CPHA = 0) ...
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... NXP Semiconductors SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 41. SPI master timing (CPHA = SPIF t SPILEAD SPICLK (CPOL = 0) (input) t SPICLK (CPOL = 1) (input) t SPIA MISO (output) t SPIDSU MOSI (input) Fig 42. SPI slave timing (CPHA = 0) P89LPC9151_61_71_2 Product data sheet ...
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... NXP Semiconductors SS t SPIF t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIOH t SPIDV t SPIA MISO not defined (output) MOSI (input) Fig 43. SPI slave timing (CPHA = 1) 12. Other characteristics 12.1 Comparator electrical characteristics Table 20. Comparator electrical characteristics 3.6 V, unless otherwise specified. ...
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... NXP Semiconductors 12.2 ADC electrical characteristics Table 21. ADC/temperature sensor electrical characteristics 3.6 V, unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb All limits valid for an external source impedance of less than 10 k Symbol Parameter V ADC analog supply voltage ...
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... NXP Semiconductors 255 254 253 252 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. Fig 45. ADC characteristics P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 (2) 1 LSB (ideal (LSB ) IA ideal Rev. 02 — 9 February 2010 8-bit microcontroller with 8-bit ADC ...
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... NXP Semiconductors 13. Package outline TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Abbreviations Table 22. Acronym ADC BOD CPU DAC EEPROM EPROM EMI IRC LSB MSB PLL PWM RAM RC RTC SAR SCL SDA SFR SPI UART P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 Abbreviations Description Analog to Digital Converter Brownout Detection Central Processing Unit Digital to Analog Converter ...
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... NXP Semiconductors 15. Revision history Table 23. Revision history Document ID Release date P89LPC9151_61_71_2 20100209 • Modifications: Changed data sheet status to "Product data sheet". P89LPC9151_61_71_1 20091209 P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 Data sheet status Change notice Product data sheet - Preliminary data sheet - Rev. 02 — 9 February 2010 ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 7 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 9 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Functional description . . . . . . . . . . . . . . . . . . 16 7.1 Special function registers . . . . . . . . . . . . . . . . 16 7.2 Enhanced CPU ...
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... NXP Semiconductors 8.4.2 Fixed channel, continuous conversion mode . 61 8.4.3 Auto scan, single conversion mode . . . . . . . . 61 8.4.4 Auto scan, continuous conversion mode . . . . 61 8.4.5 Dual channel, continuous conversion mode . . 62 8.4.6 Single step mode . . . . . . . . . . . . . . . . . . . . . . 62 8.5 Conversion start modes . . . . . . . . . . . . . . . . . 62 8.5.1 Timer triggered start . . . . . . . . . . . . . . . . . . . . 62 8.5.2 Start immediately . . . . . . . . . . . . . . . . . . . . . . 62 8 ...