P89LPC972FDH,129 NXP Semiconductors, P89LPC972FDH,129 Datasheet
P89LPC972FDH,129
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P89LPC970/971/972 8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB wide-voltage byte-erasable flash Rev. 3 — 8 June 2010 1. General description The P89LPC970/971/972 is a single-chip microcontroller, available in low cost packages, based on a high performance ...
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... NXP Semiconductors 2.2 Additional features A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI ...
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... NXP Semiconductors 3. Ordering information Table 1. Type number P89LPC970FDH P89LPC971FDH P89LPC972FDH P89LPC972FN 3.1 Ordering options Table 2. Type number P89LPC970FDH P89LPC971FDH P89LPC972FDH P89LPC972FN P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Ordering information Package Name Description TSSOP20 plastic thin shrink small outline package; 20 leads ...
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... NXP Semiconductors 4. Block diagram P89LPC970/971/972 P3[1:0] P1[7:0] P0[7:0] XTAL1 CRYSTAL OR RESONATOR XTAL2 (1) For pin remap Fig 1. Block diagram P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core ACCELERATED 2-CLOCK 80C51 CPU 2 kB/4 kB/8 kB CODE FLASH internal bus 256-BYTE DATA RAM ...
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... NXP Semiconductors 5. Functional diagram (1) SPICLK KBI0 KBI1 KBI2 T2 KBI3 KBI4 T3 KBI5 CMPREF KBI6 KBI7 CLKOUT (1) For pin remap Fig 2. Functional diagram P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core CMP2 CIN2B CIN2A CIN1B PORT 0 CIN1A P89LPC970/ 971/972 CMP1 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Fig 4. P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core P0.0/CMP2/KBI0/SPICLK 1 P1.7/T3EX/MOSI 2 3 P1.6/MISO 4 P1.5/RST P89LPC970/971/972 P3.1/XTAL1 6 P3.0/XTAL2/CLKOUT 7 8 P1.4/INT1/T4EX/SS 9 P1.3/INT0/SDA/T4 P1.2/SCL/T0 10 TSSOP20 pin configuration P0.0/CMP2/KBI0/SPICLK 1 P1.7/T3EX/MOSI 2 P1.6/MISO 3 P1.5/RST P3.1/XTAL1 7 P3.0/XTAL2/CLKOUT 8 P1.4/INT1/T4EX/ ...
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... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin DIP20, TSSOP20 P0.0 to P0.7 P0.0/CMP2/KBI0/ 1 SPICLK P0.1/CIN2B/ 20 KBI1 P0.2/CIN2A/ 19 KBI2 P0.3/CIN1B/ 18 KBI3/T2 P0.4/CIN1A/ 17 KBI4 P0.5/CMPREF/ 16 KBI5/T3 P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O Port 0: Port 8-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input-only mode with the internal pull-up disabled ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin DIP20, TSSOP20 P0.6/CMP1/KBI6 14 P0.7/KBI7/T1 13 P1.0 to P1.7 P1.0/TXD 12 P1.1/RXD/T2EX 11 P1.2/SCL/T0 10 P1.3/INT0/SDA P1.4/INT1/T4EX P1.5/RST 4 P1.6/MISO 3 P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O P0.6 — Port 0 bit 6. High current source. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin DIP20, TSSOP20 P1.7/T3EX/MOSI 2 P3.0 to P3.1 P3.0/XTAL2/ 7 CLKOUT P3.1/XTAL1 [1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5. P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O P1.7 — Port 1 bit 7. High current source. ...
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... NXP Semiconductors 7. Functional description Remark: Please refer to the P89LPC970/971/972 User manual for a more detailed functional description. 7.1 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. ...
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Table 4. Special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 ACC* Accumulator E0H AUXR1 Auxiliary A2H CLKLP function register Bit address register F0H ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB FMCON Program flash E4H BUSY control (Read) Program flash E4H FMCMD. control (Write) 7 FMDATA Program flash E5H ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address FF IP1* Interrupt F8H - priority 1 IP1H Interrupt F7H - priority 1 high KBCON Keypad ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB PCON Power control 87H SMOD1 register PCONA Power control B5H RTCPD register A PINCON pin remap CFH - ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB RCAP2L Capture register FBH 2 low byte RCAP3H Capture register ECH 3 high byte RCAP3L Capture register EBH ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB SPSTAT SPI status E1H SPIF register SPDAT SPI data E3H register TAMOD Timer 0 and 1 8FH - ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB TH4 Timer/Counter 4 CCH high byte TL4 Timer/Counter 4 CBH low byte TINTF Timer/Counters CEH - 2/3/4 overflow ...
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Table 5. Extended special function registers Name Description SFR addr. Bit functions and addresses MSB BODCFG BOD FFC8H - configuration register CLKCON Clock control FFDEH CLKOK register CMPREF Comparator FFCBH - reference register RTCDAT Real-time FFBFH H clock data register ...
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... NXP Semiconductors 7.2 Enhanced CPU The P89LPC970/971/972 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 7.3 Clocks 7.3.1 Clock definitions The P89LPC970/971/972 device has several internal clocks as defined below: OSCCLK — ...
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... NXP Semiconductors 7.5 Clock output The P89LPC970/971/972 supports a user-selectable clock output function on the P3.0/XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on XTAL1) and if the RTC and WDT are not using the crystal oscillator as their clock source ...
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... NXP Semiconductors HIGH FREQUENCY XTAL1 MEDIUM FREQUENCY XTAL2 LOW FREQUENCY RC OSCILLATOR WITH CLOCK DOUBLER (7.3728 MHz/14.7456 MHz ± WATCHDOG OSCILLATOR (400 kHz/25 kHz ± (1) ± 400 kHz. Fig 5. Block diagram of oscillator control 7.10 CCLK wake-up delay The P89LPC970/971/972 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used ...
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... NXP Semiconductors 7.13 Memory organization The various P89LPC970/971/972 memory spaces are as follows: • DATA 128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. ...
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... NXP Semiconductors not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced ...
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... NXP Semiconductors RTCF ERTC WDOVF TF2 EXF2 TIEN2 TF3 EXF3 TIEN3 TF4 EXF4 TIEN4 EXTIM (1) For pin remap. Fig 6. Interrupt sources, interrupt enables, and power-down wake-up sources P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core IE0 EX0 IE1 ...
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... NXP Semiconductors 7.16 I/O ports The P89LPC970/971/972 has four I/O ports: Port 0, Port 1 and Port 3. Ports 0, 1 are 8-bit ports, and Port 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 7. Clock source ...
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... NXP Semiconductors 7.16.1.3 Input-only configuration The input-only port configuration has no output drivers Schmitt trigger input that also has a glitch suppression circuit. 7.16.1.4 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1 ...
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... NXP Semiconductors Table 8. Peripherals SPI I2C UART 7.17 Power management The P89LPC970/971/972 support a variety of power management features. Power-on detect and brownout detect are designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. The P89LPC970/971/972 support three different power reduction modes: Idle mode, Power-down mode, and total Power-down mode ...
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... NXP Semiconductors 7.17.2 Power-on detection The Power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially to ensure that the device is reset from Power-on. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software ...
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... NXP Semiconductors 7.18 Reset The P1.5/RST pin can function as either a LOW-active reset input digital input, P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. ...
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... NXP Semiconductors In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its corresponding count input pin T1. In this function, the count input is sampled once during every machine cycle. Timer 0 and Timer 1 have five operating modes (Modes and 6). Modes and 6 are the same for both Timers/Counters. Mode 3 is different. ...
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... NXP Semiconductors 7.20.1 Mode 0: 16-bit timer/counter with auto-reload Mode 0 configures the timer register as an 16-bit Timer/counter with automatic reload. An overflow upon the timer or a 1-to-0 transition at TxEX pin can cause the reload event. 7.20.2 Mode 1: 16-bit timer/counter with input capture Mode 1 configures the timer register as an 16-bit Timer/counter with input capture. A 1-to-0 transition at TxEX pin can cause the capture event ...
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... NXP Semiconductors 7.22.2 Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in special function register SCON. The baud rate is variable and is determined by ...
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... NXP Semiconductors 7.22.7 Break detect Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode. 7.22.8 Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SnBUF while the first character is being transmitted ...
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... NXP Semiconductors Fig 8. P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 2 I C-bus P1.3/SDA P1.2/SCL P89LPC970/971/972 2 I C-bus configuration All information provided in this document is subject to legal disclaimers. Rev. 3 — 8 June 2010 P89LPC970/971/972 OTHER DEVICE OTHER DEVICE 2 2 WITH I ...
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... NXP Semiconductors P1.3/SDA P1.2/SCL Fig 9. P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core P1.3 INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL status bus I2STAT 2 I C-bus serial interface block diagram All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 7.24 SPI (Pin remap) The P89LPC970/971/972 provides another high-speed serial communication interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode Mbit/s can be supported in either Master mode or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection ...
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... NXP Semiconductors 7.24.1 Typical SPI configurations Fig 11. SPI single master single slave configuration Fig 12. SPI dual device configuration, where either can be a master or a slave P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core master MISO 8-BIT SHIFT MOSI ...
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... NXP Semiconductors Fig 13. SPI single master multiple slaves configuration 7.25 Analog comparators Two analog comparators are provided on the P89LPC970/971/972. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage) ...
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... NXP Semiconductors (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF (1) V ref(cmp) (P0.2) CIN2A (P0.1) CIN2B (1) See Section 7.25.1 for more details. Fig 14. Comparator input and output connections 7.25.1 Selectable internal reference voltage An internal reference voltage generator may be used to supply a default reference when a single comparator input pin is used ...
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... NXP Semiconductors 7.26 KBI The Keypad Interrupt function (KBI) is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The port can be configured via SFRs for different tasks ...
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... NXP Semiconductors MOV WFEED1, #0A5H MOV WFEED2, #05AH 400 kHz PCLK 0 oscillator kHz crystal 1 watchdog oscillator oscillator oscillator WDMOD (CLKCON.5) (1) Watchdog reset can also be caused by an invalid feed sequence writing to WDCON not immediately followed by a feed sequence. Fig 15. Watchdog timer in Watchdog mode (WDTE = 1) 7 ...
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... NXP Semiconductors optimize the erase and programming mechanisms. The P89LPC970/971/972 uses V the supply voltage to perform the Program/Erase algorithms. When voltage supply is lower than 2.4 V, the BOD flash is tripped and flash erase/program is blocked. 7.29.2 Features • Programming and erase over the full operating voltage range. ...
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... NXP Semiconductors 7.29.6 ICP ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC970/971/972 through a two-wire serial interface. The NXP ICP facility has made in-circuit programming in an embedded application - using commercially available programmers - possible with a minimum of additional expense in components and circuit board area ...
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... NXP Semiconductors Remark: Users who wish to use this loader should take precautions to avoid erasing the 1 kB sector that contains this bootloader. Instead, the page erase function can be used to erase the first eight 64-byte pages located in this sector. A custom bootloader can be written with the Boot Vector set to the custom bootloader, if desired ...
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... NXP Semiconductors 8. Limiting values Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter T bias ambient temperature amb(bias) T storage temperature stg I HIGH-level output current per OH(I/O) input/output pin I LOW-level output current per OL(I/O) input/output pin I maximum total input/output current ...
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... NXP Semiconductors system frequency (MHz 2.4 Fig 16. Frequency vs. supply voltage P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 2.7 3.0 3.3 3.6 All information provided in this document is subject to legal disclaimers. Rev. 3 — 8 June 2010 P89LPC970/971/972 V (V) DD © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 9. Static characteristics Table 11. Static characteristics 5.5 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter Conditions I operating supply V DD(oper) current Idle mode supply V DD(idle) current Power-down mode V DD(pd) supply current powered down ...
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... NXP Semiconductors Table 11. Static characteristics 5.5 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter Conditions I total Power-down V DD(tpd) mode supply V current V (dV/dt) rise rate (dV/dt) fall rate power-on reset POR voltage V data retention ...
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... NXP Semiconductors Table 11. Static characteristics 5.5 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter Conditions R internal pull-up pin RST RST_N(int) resistance on pin RST BOD interrupt V trip voltage falling stage trip rising stage ...
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... NXP Semiconductors Table 11. Static characteristics 5.5 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter Conditions BOD reset V trip voltage falling stage trip rising stage BOD flash V trip voltage falling stage trip rising stage ...
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... NXP Semiconductors 10. Dynamic characteristics Table 12. Dynamic characteristics (12 MHz 2 5.5 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter f internal RC oscillator osc(RC) frequency f internal watchdog osc(WD) oscillator frequency f oscillator frequency osc T clock cycle time cy(clk) ...
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... NXP Semiconductors Table 12. Dynamic characteristics (12 MHz 2 5.5 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter T SPI cycle time SPICYC slave master t SPI enable lead time SPILEAD slave t SPI enable lag time SPILAG slave ...
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... NXP Semiconductors Table 13. Dynamic characteristics (18 MHz 3 5.5 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter f internal RC oscillator osc(RC) frequency f internal watchdog osc(WD) oscillator frequency f oscillator frequency osc T clock cycle time cy(clk) f low-power select clock ...
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... NXP Semiconductors Table 13. Dynamic characteristics (18 MHz 3 5.5 V unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter t SPI enable lead time SPILEAD slave t SPI enable lag time SPILAG slave t SPICLK HIGH time SPICLKH slave master ...
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... NXP Semiconductors 10.1 Waveforms Fig 17. External clock timing (with an amplitude of at least V clock t QVXH output data write to SBUF t XHDV input data clear RI Fig 18. Shift register mode timing SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t MOSI SPIF (output) Fig 19. SPI master timing (CPHA = 0) ...
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... NXP Semiconductors SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 20. SPI master timing (CPHA = SPIF t SPILEAD SPICLK (CPOL = 0) (input) t SPICLK (CPOL = 1) (input) t SPIA MISO (output) t SPIDSU MOSI (input) Fig 21. SPI slave timing (CPHA = 0) P89LPC97X Product data sheet ...
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... NXP Semiconductors SS t SPIF t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIOH t SPIDV t SPIA MISO not defined (output) MOSI (input) Fig 22. SPI slave timing (CPHA = 1) 10.2 ISP entry mode Table 14. Dynamic characteristics, ISP entry mode 5.5 V, unless otherwise specified. ...
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... NXP Semiconductors 11. Other characteristics 11.1 Comparator electrical characteristics Table 15. Comparator electrical characteristics 5.5 V, unless otherwise specified. DD − ° ° +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter V input offset voltage IO V common-mode input voltage IC CMRR common-mode rejection ratio ...
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... NXP Semiconductors 12. Package outline TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DIP20: plastic dual in-line package; 20 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors 13. Abbreviations Table 16. Acronym CCU CPU CRC DAC EEPROM EMI EPROM GPIO IRC LSB MSB PGA PLL PWM RAM RC RTC SAR SFR SPI UART WDT P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Abbreviations Description Capture/Compare Unit ...
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... NXP Semiconductors 14. Revision history Table 17. Revision history Document ID Release date P89LPC97X v.3 20100608 • Modifications: Section 7.4 “Crystal oscillator option” on page • Section 7.27 “Watchdog timer” on page P89LPC97X_2 20100427 • Modifications: Changed data sheet status to ‘Product data sheet’. ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... P89LPC97X Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . 10 7.1 Special function registers . . . . . . . . . . . . . . . . 10 7 ...
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... NXP Semiconductors 7.29.3 Flash organization . . . . . . . . . . . . . . . . . . . . . 42 7.29.4 Using flash as data storage . . . . . . . . . . . . . . 42 7.29.5 Flash programming and erasing . . . . . . . . . . . 42 7.29.6 ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.29.7 IAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.29.8 ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.29.9 Power-on reset code execution . . . . . . . . . . . 43 7.29.10 Hardware activation of the bootloader . . . . . . 44 7.30 User configuration bytes . . . . . . . . . . . . . . . . . 44 7.31 User sector security bytes . . . . . . . . . . . . . . . 44 8 Limiting values Static characteristics ...