P89LPC931A1FDH,512 NXP Semiconductors, P89LPC931A1FDH,512 Datasheet
P89LPC931A1FDH,512
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P89LPC9301/931A1 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB byte-erasable flash Rev. 2 — 29 November 2010 1. General description The P89LPC9301/931A1 is a single-chip microcontroller, available in low cost packages, based on a high performance ...
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... NXP Semiconductors Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application. In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application. Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to 5 %, ...
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... NXP Semiconductors 3. Ordering information Table 1. Type number P89LPC9301FDH P89LPC931A1FDH 3.1 Ordering options Table 2. Type number P89LPC9301FDH P89LPC931A1FDH P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Ordering information Package Name Description TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm TSSOP28 plastic thin shrink small outline package ...
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... NXP Semiconductors 4. Block diagram P89LPC9301/931A1 P3[1:0] CONFIGURABLE I/Os P2[7:0] CONFIGURABLE I/Os P1[7:0] CONFIGURABLE I/Os P0[7:0] CONFIGURABLE I/Os PROGRAMMABLE OSCILLATOR DIVIDER XTAL1 CRYSTAL OR RESONATOR XTAL2 Fig 1. Block diagram P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU ...
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... NXP Semiconductors 5. Functional diagram KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 CLKOUT Fig 2. Functional diagram P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core V DD CMP2 CIN2B CIN2A CIN1B PORT 0 CIN1A CMPREF CMP1 T1 P89LPC9301/ 931A1 XTAL2 PORT 3 XTAL1 002aae448 All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core P2 P2.1 3 P0.0/CMP2/KBI0 P1.7 4 P1.6 5 P1.5/RST P89LPC9301FDH SS P89LPC931A1FDH 8 P3.1/XTAL1 P3.0/XTAL2/CLKOUT 9 P1.4/INT1 10 P1.3/INT0/SDA 11 12 P1.2/T0/SCL 13 P2.2/MOSI 14 P2.3/MISO P89LPC9301/931A1 TSSOP28 pin configuration All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin P0.0 to P0.7 P0.0/CMP2/ 3 KBI0 P0.1/CIN2B/ 26 KBI1 P0.2/CIN2A/ 25 KBI2 P0.3/CIN1B/ 24 KBI3 P0.4/CIN1A/ 23 KBI4 P0.5/CMPREF/ 22 KBI5 P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O Port 0: Port 8-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin P0.6/CMP1/KBI6 20 P0.7/T1/KBI7 19 P1.0 to P1.7 P1.0/TXD 18 P1.1/RXD 17 P1.2/T0/SCL 12 P1.3/INT0/SDA 11 P1.4/INT1 10 P1.5/RST 6 P1.6 5 P1.7 4 P2.0 to P2.7 P2.0 1 P2.1 2 P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O P0.6 — Port 0 bit 6. High current source. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin P2.2/MOSI 13 P2.3/MISO 14 P2.4/SS 15 P2.5/SPICLK 16 P2.6 27 P2.7 28 P3.0 to P3.1 P3.0/XTAL2/ 9 CLKOUT P3.1/XTAL1 [1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5. P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O P2.2 — ...
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... NXP Semiconductors 7. Functional description Remark: Please refer to the P89LPC9301/931A1 User manual for a more detailed functional description. 7.1 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. ...
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Table 4. Special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 ACC* Accumulator E0H AUXR1 Auxiliary A2H CLKLP function register Bit address register F0H ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB FMCON Program flash E4H BUSY control (Read) Program flash E4H FMCMD.7 control (Write) FMDATA Program flash E5H data ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address BF IP0* Interrupt B8H - priority 0 IP0H Interrupt B7H - priority 0 high Bit address ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB P1M2 Port 1 output 92H (P1M2.7) mode 2 P2M1 Port 2 output A4H (P2M1.7) mode 1 P2M2 Port ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address 9F SCON* Serial port 98H SM0/FE control SSTAT Serial port BAH DBMOD extended status register SP ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB WDL Watchdog load C1H WFEED1 Watchdog C2H feed 1 WFEED2 Watchdog C3H feed 2 [1] All ports are ...
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Table 5. Extended special function registers Name Description SFR Bit functions and addresses addr. BODCFG BOD FFC8H configuration register CLKCON CLOCK Control FFDEH CLKOK register RTCDATH Real-time clock FFBFH data register high RTCDATL Real-time clock FFBEH data register low [1] ...
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... NXP Semiconductors 7.2 Enhanced CPU The P89LPC9301/931A1 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 7.3 Clocks 7.3.1 Clock definitions The P89LPC9301/931A1 device has several internal clocks as defined below: OSCCLK — ...
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... NXP Semiconductors 7.5 Clock output The P89LPC9301/931A1 supports a user-selectable clock output function on the P3.0/XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on XTAL1) and if the RTC and WDT are not using the crystal oscillator as their clock source ...
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... NXP Semiconductors XTAL1 MEDIUM FREQUENCY XTAL2 RC OSCILLATOR WITH CLOCK DOUBLER (7.3728 MHz/14.7456 MHz ± WATCHDOG OSCILLATOR (400 kHz ± Fig 4. Block diagram of oscillator control 7.10 CCLK wake-up delay The P89LPC9301/931A1 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60 ...
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... NXP Semiconductors 7.13 Memory organization The various P89LPC9301/931A1 memory spaces are as follows: • DATA 128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. ...
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... NXP Semiconductors If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level. 7.15.1 External interrupt inputs The P89LPC9301/931A1 has two external interrupt inputs as well as the Keypad Interrupt function ...
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... NXP Semiconductors 7.16 I/O ports The P89LPC9301/931A1 has four I/O ports: Port 0, Port 1, Port 2 and Port 3. Ports 0, 1, and 2 are 8-bit ports, and Port 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 7 ...
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... NXP Semiconductors An open-drain port pin has a Schmitt trigger input that also has a glitch suppression circuit. 7.16.1.3 Input-only configuration The input-only port configuration has no output drivers Schmitt trigger input that also has a glitch suppression circuit. 7.16.1.4 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1 ...
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... NXP Semiconductors 7.17.1 Brownout detection The brownout detect function determines if the power supply voltage drops below a certain level. Enhanced brownout detection has 3 independent functions: BOD reset, BOD interrupt and BOD FLASH. BOD reset is always on except in total Power-down mode. It could not be disabled in software ...
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... NXP Semiconductors 7.18.3 Total Power-down mode This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled ...
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... NXP Semiconductors The boot address will be used if a UART break reset occurs, or the non-volatile boot status bit (BOOTSTAT. the device is forced into ISP mode during power-on (see P89LPC9301/931A1 User manual). Otherwise, instructions will be fetched from address 0000H. 7.20 Timers/counters 0 and 1 The P89LPC9301/931A1 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1 ...
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... NXP Semiconductors 7.21 RTC/system timer The P89LPC9301/931A1 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake- interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter ...
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... NXP Semiconductors 7.22.4 Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9 the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the baud rate generator (described in Section 7.22.5 “ ...
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... NXP Semiconductors 7.22.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3) Unlike the conventional UART, in double buffering mode, the TI interrupt is generated when the double buffer is ready to receive new data. th 7.22.10 The 9 If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out ...
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... NXP Semiconductors P1.3/SDA P1.2/SCL Fig 8. P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core P1.3 INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL status bus I2STAT 2 I C-bus serial interface block diagram All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 7.24 SPI The P89LPC9301/931A1 provides another high-speed serial communication interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode Mbit/s can be supported in either Master mode or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection ...
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... NXP Semiconductors 7.24.1 Typical SPI configurations Fig 10. SPI single master single slave configuration Fig 11. SPI dual device configuration, where either can be a master or a slave P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core master MISO 8-BIT SHIFT MOSI ...
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... NXP Semiconductors Fig 12. SPI single master multiple slaves configuration 7.25 Analog comparators Two analog comparators are provided on the P89LPC9301/931A1. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable inputs) is greater than the negative input (selectable from a pin or an internal reference voltage) ...
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... NXP Semiconductors (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF V ref(bg) (P0.2) CIN2A (P0.1) CIN2B Fig 13. Comparator input and output connections 7.25.1 Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred 1.23 V ...
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... NXP Semiconductors 7.26 KBI The Keypad Interrupt function (KBI) is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks ...
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... NXP Semiconductors MOV WFEED1, #0A5H MOV WFEED2, #05AH PCLK 0 0 watchdog 1 crystal oscillator 1 oscillator XTALWD WDCON (A7H) (1) Watchdog reset can also be caused by an invalid feed sequence writing to WDCON not immediately followed by a feed sequence. Fig 14. Watchdog timer in Watchdog mode (WDTE = 1) 7.28 Additional features 7 ...
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... NXP Semiconductors optimize the erase and programming mechanisms. The P89LPC9301/931A1 uses V the supply voltage to perform the Program/Erase algorithms. When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and flash erase/program is blocked. 7.29.2 Features • Programming and erase over the full operating voltage range. ...
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... NXP Semiconductors 7.29.6 ICP ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC9301/931A1 through a two-wire serial interface. The NXP ICP facility has made in-circuit programming in an embedded application - using commercially available programmers - possible with a minimum of additional expense in components and circuit board area ...
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... NXP Semiconductors Remark: Users who wish to use this loader should take precautions to avoid erasing the 1 kB sector that contains this bootloader. Instead, the page erase function can be used to erase the first eight 64-byte pages located in this sector. A custom bootloader can be written with the Boot Vector set to the custom bootloader, if desired ...
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... NXP Semiconductors 8. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter T bias ambient temperature amb(bias) T storage temperature stg I HIGH-level output current per OH(I/O) input/output pin I LOW-level output current per OL(I/O) input/output pin I maximum total input/output current ...
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... NXP Semiconductors 9. Static characteristics Table 10. Static characteristics 3.6 V unless otherwise specified. DD +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter I operating supply current DD(oper) I Idle mode supply current DD(idle) I Power-down mode supply DD(pd) current I total Power-down mode ...
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... NXP Semiconductors Table 10. Static characteristics 3.6 V unless otherwise specified. DD +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter I HIGH-LOW transition THL current R internal pull-up resistance RST_N(int) on pin RST V band gap reference voltage ref(bg) TC band gap temperature ...
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... NXP Semiconductors 9.1 Current characteristics Note: The graphs provided are a statistical summary based on a limited number of samples and only for information purposes. The performance characteristics listed are not tested or guaranteed. (mA) Fig 16. I (mA) Fig 17. I P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core ...
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... NXP Semiconductors (mA) Fig 18. I (mA) Fig 19. I P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 2.4 2.8 Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock. vs. frequency at +85 C DD(oper) 5 4.0 3.0 2.0 1.0 0.0 2 ...
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... NXP Semiconductors (mA) Fig 20. I (mA) Fig 21. I P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 5 4.0 3.0 2.0 1.0 0.0 2.4 2.8 Test conditions: Idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. ...
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... NXP Semiconductors (μA) (1) +85 C (2) +25 C (3) 40 C Fig 22. I (μA) (1) +85 C (2) 40 C (3) +25 C Fig 23. I P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 20 18.0 16.0 14.0 12.0 10.0 2.4 2.8 Test conditions: Power-down mode, using internal RC oscillator with the following functions disabled: comparators, real-time clock, and watchdog timer ...
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... NXP Semiconductors 9.2 Internal RC/watchdog oscillator characteristics Note: The graphs provided are a statistical summary based on a limited number of samples and only for information purposes. The performance characteristics listed are not tested or guaranteed. frequency deviation (%) Fig 24. Average internal RC oscillator frequency vs. V frequency ...
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... NXP Semiconductors frequency deviation (%) Fig 26. Average internal RC oscillator frequency vs. V frequency deviation (%) Fig 27. Average watchdog oscillator frequency vs. V P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 0.2 0 −0.2 −0.4 −0.6 2.4 2.8 Central frequency of internal RC oscillator = 7.3728 MHz 2 ...
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... NXP Semiconductors frequency deviation (%) Fig 28. Average watchdog oscillator frequency vs. V frequency deviation (%) Fig 29. Average watchdog oscillator frequency vs. V P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 0.5 −0.5 −1.5 −2.5 −3.5 2.4 2.8 Central frequency of watchdog oscillator = 400 kHz 1 ...
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... NXP Semiconductors 9.3 BOD characteristics Table 11. BOD static characteristics 3.6 V unless otherwise specified. DD +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter BOD interrupt V trip voltage trip BOD reset V trip voltage trip BOD EEPROM/flash V trip voltage ...
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... NXP Semiconductors 10. Dynamic characteristics Table 12. Dynamic characteristics (12 MHz 2 3.6 V unless otherwise specified. DD +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter f internal RC oscillator osc(RC) frequency f internal watchdog osc(WD) oscillator frequency f oscillator frequency osc T clock cycle time cy(clk) ...
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... NXP Semiconductors Table 12. Dynamic characteristics (12 MHz 2 3.6 V unless otherwise specified. DD +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter T SPI cycle time SPICYC slave master t SPI enable lead time SPILEAD slave t SPI enable lag time SPILAG slave ...
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... NXP Semiconductors Table 13. Dynamic characteristics (18 MHz 3 3.6 V unless otherwise specified. DD +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter f internal RC oscillator osc(RC) frequency f internal watchdog osc(WD) oscillator frequency f oscillator frequency osc T clock cycle time cy(clk) f low-power select clock ...
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... NXP Semiconductors Table 13. Dynamic characteristics (18 MHz 3 3.6 V unless otherwise specified. DD +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter t SPI enable lead time SPILEAD slave t SPI enable lag time SPILAG slave t SPICLK HIGH time SPICLKH slave master ...
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... NXP Semiconductors 10.1 Waveforms clock t QVXH output data write to SBUF t XHDV input data clear RI Fig 31. Shift register mode timing Fig 32. External clock timing (with an amplitude of at least V SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t MOSI SPIF (output) Fig 33. SPI master timing (CPHA = 0) ...
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... NXP Semiconductors SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 34. SPI master timing (CPHA = SPIF t SPILEAD SPICLK (CPOL = 0) (input) t SPICLK (CPOL = 1) (input) t SPIA MISO (output) t SPIDSU MOSI (input) Fig 35. SPI slave timing (CPHA = 0) P89LPC9301_931A1 Product data sheet ...
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... NXP Semiconductors SS t SPIF t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIOH t SPIDV t SPIA MISO not defined (output) MOSI (input) Fig 36. SPI slave timing (CPHA = 1) 10.2 ISP entry mode Table 14. Dynamic characteristics, ISP entry mode 3.6 V, unless otherwise specified. ...
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... NXP Semiconductors 11. Other characteristics 11.1 Comparator electrical characteristics Table 15. Comparator electrical characteristics 3.6 V, unless otherwise specified. DD +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter V input offset voltage IO V common-mode input voltage IC CMRR common-mode rejection ratio ...
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... NXP Semiconductors 12. Package outline TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Abbreviations Table 16. Acronym BOD CPU CRC EPROM EEPROM EMI LSB MSB PWM RAM RC RTC SCL SDA SFR SPI UART WDT P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Abbreviations Description Brownout Detection Central Processing Unit Cyclic Redundancy Check ...
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... NXP Semiconductors 14. Revision history Table 17. Revision history Document ID Release date P89LPC9301_931A1 v.2 20101129 • Modifications: Section • Section • Table • Table • Changed data sheet status to Product. P89LPC9301_931A1 v.1 20090409 P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... P89LPC9301_931A1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . 10 7.1 Special function registers . . . . . . . . . . . . . . . . 10 7 ...
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... NXP Semiconductors 7.31 User sector security bytes . . . . . . . . . . . . . . . 40 8 Limiting values Static characteristics 9.1 Current characteristics . . . . . . . . . . . . . . . . . . 44 9.2 Internal RC/watchdog oscillator characteristics 48 9.3 BOD characteristics . . . . . . . . . . . . . . . . . . . . 51 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 52 10.1 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2 ISP entry mode . . . . . . . . . . . . . . . . . . . . . . . . 58 11 Other characteristics . . . . . . . . . . . . . . . . . . . . 59 11.1 Comparator electrical characteristics . . . . . . . 59 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 60 13 Abbreviations ...