P89LPC9341FDH,512 NXP Semiconductors, P89LPC9341FDH,512 Datasheet

IC 80C51 MCU FLASH 8K 28-TSSOP

P89LPC9341FDH,512

Manufacturer Part Number
P89LPC9341FDH,512
Description
IC 80C51 MCU FLASH 8K 28-TSSOP
Manufacturer
NXP Semiconductors
Series
LPC900r
Datasheet

Specifications of P89LPC9341FDH,512

Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
28-TSSOP
Core Processor
8051
Core Size
8-Bit
Speed
18MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x8b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
P89LPC
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
18 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8 bit, 4 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
935288632512
1. General description
2. Features and benefits
2.1 Principal features
The P89LPC9331/9341/9351/9361 is a single-chip microcontroller, available in low cost
packages, based on a high performance processor architecture that executes instructions
in two to four clocks, six times the rate of standard 80C51 devices. Many system-level
functions have been incorporated into the P89LPC9331/9341/9351/9361 in order to
reduce component count, board space, and system cost.
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core,
4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs
Rev. 5 — 10 January 2011
4 kB/8 kB/16 kB byte-erasable flash code memory organized into 1 kB sectors and
64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data
storage.
256-byte RAM data memory. P89LPC9351 and P89LPC9361 also include a 512-byte
auxiliary on-chip RAM.
512-byte customer data EEPROM on-chip allows serialization of devices, storage of
setup parameters, etc. (P89LPC9351/9361)
Dual 4-input multiplexed 8-bit ADC/DAC outputs. Two analog comparators with
selectable inputs and reference source.
Dual Programmable Gain Amplifiers (PGA) with selectable gains of 2x, 4x, 8x, or 16x
can be applied to ADCs and analog comparator inputs. (P89LPC9351/9361)
On-chip temperature sensor integrated with ADC module.
Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output).
A 23-bit system timer that can also be used as a real-time clock consisting of a 7-bit
prescaler and a programmable and readable 16-bit timer.
Enhanced UART with a fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I
communication port and SPI communication port.
Capture/Compare Unit (CCU) provides PWM, input capture, and output compare
functions. (P89LPC9351/9361)
2.4 V to 3.6 V V
driven to 5.5 V).
Enhanced low voltage (brownout) detect allows a graceful system shutdown when
power fails.
28-pin TSSOP and PLCC packages with 23 I/O pins minimum and up to 26 I/O pins
while using on-chip oscillator and reset options.
DD
operating range. I/O pins are 5 V tolerant (may be pulled up or
Product data sheet
2
C-bus

Related parts for P89LPC9341FDH,512

P89LPC9341FDH,512 Summary of contents

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P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB/8 kB/ byte-erasable flash with 8-bit ADCs Rev. 5 — 10 January 2011 1. General description The P89LPC9331/9341/9351/9361 is a single-chip microcontroller, available in low cost packages, based ...

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... NXP Semiconductors 2.2 Additional features A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI ...

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... NXP Semiconductors 3. Ordering information Table 1. Type number P89LPC9331FDH P89LPC9331HDH P89LPC9341FDH P89LPC9351FA P89LPC9351FDH P89LPC9361FDH 3.1 Ordering options Table 2. Type number P89LPC9331FDH P89LPC9331HDH P89LPC9341FDH P89LPC9351FA P89LPC9351FDH P89LPC9361FDH P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core Ordering information Package Name ...

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... NXP Semiconductors 4. Block diagram P89LPC9331/9341/9351/9361 P3[1:0] P2[7:0] P1[7:0] P0[7:0] XTAL1 CRYSTAL OR RESONATOR XTAL2 (1) P89LPC9351/9361 (2) PGA1 on P89LPC9351/9361 (3) PGA0 on P89LPC9351/9361 Fig 1. Block diagram P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core ACCELERATED 2-CLOCK 80C51 CPU 4 kB/8 kB/16 kB CODE FLASH ...

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... NXP Semiconductors 5. Functional diagram KBI0 AD01 KBI1 AD10 KBI2 AD11 KBI3 AD12 KBI4 DAC1 AD13 KBI5 KBI6 KBI7 CLKOUT Fig 2. Functional diagram (P89LPC9331/9341) KBI0 AD01 KBI1 AD10 KBI2 AD11 KBI3 AD12 DAC1 KBI4 AD13 KBI5 KBI6 KBI7 CLKOUT Fig 3. Functional diagram (P89LPC9351/9361) ...

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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 4. Fig 5. P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core P2.0/AD03/DAC0 1 2 P2.1/AD02 3 P0.0/CMP2/KBI0/AD01 4 P1.7/AD00 P1.6 5 P1.5/RST P89LPC9331FDH/ 8 P3.1/XTAL1 P89LPC9341FDH 9 P3.0/XTAL2/CLKOUT P1.4/INT1 10 P1.3/INT0/SDA 11 12 P1.2/T0/SCL 13 P2.2/MOSI 14 P2.3/MISO P89LPC9331/9341 TSSOP28 pin configuration P2 ...

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... NXP Semiconductors Fig 6. P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core 5 P1.6/OCB P1.5/RST P3.1/XTAL1 8 P89LPC9351FA 9 P3.0/XTAL2/CLKOUT P1.4/INT1 10 P1.3/INT0/SDA 11 P89LPC9351 PLCC28 pin configuration All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 January 2011 25 P0.2/CIN2A/KBI2/AD11 24 P0.3/CIN1B/KBI3/AD12 23 P0.4/CIN1A/KBI4/DAC1/AD13 22 P0 ...

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... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin PLCC28, TSSOP28 P0.0 to P0.7 P0.0/CMP2/ 3 KBI0/AD01 P0.1/CIN2B/ 26 KBI1/AD10 P0.2/CIN2A/ 25 KBI2/AD11 P0.3/CIN1B/ 24 KBI3/AD12 P0.4/CIN1A/ 23 KBI4/DAC1/AD13 P0.5/CMPREF/ 22 KBI5 P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O Port 0: Port 8-bit I/O port with a user-configurable output type ...

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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin PLCC28, TSSOP28 P0.6/CMP1/KBI6 20 P0.7/T1/KBI7 19 P1.0 to P1.7 P1.0/TXD 18 P1.1/RXD 17 P1.2/T0/SCL 12 P1.3/INT0/SDA 11 P1.4/INT1 10 P1.5/RST 6 P1.6/OCB 5 P1.7/OCC/AD00 4 P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O P0.6 — Port 0 bit 6. High current source. ...

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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin PLCC28, TSSOP28 P2.0 to P2.7 P2.0/ICB/DAC0 1 /AD03 P2.1/OCD/AD02 2 P2.2/MOSI 13 P2.3/MISO 14 P2.4/SS 15 P2.5/SPICLK 16 P2.6/OCA 27 P2.7/ICA 28 P3.0 to P3.1 P3.0/XTAL2/ 9 CLKOUT P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O Port 2: Port 8-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled ...

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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin PLCC28, TSSOP28 P3.1/XTAL1 [1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5. P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O P3.1 — Port 3 bit 1. I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration) ...

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... NXP Semiconductors 7. Functional description Remark: Please refer to the P89LPC9331/9341/9351/9361 User manual for a more detailed functional description. 7.1 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. ...

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Table 4. Special function registers - P89LPC9331/9341 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 ACC* Accumulator E0H ADCON0 A/D control 8EH ENBI0 register 0 ADCON1 A/D control 97H ...

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Table 4. Special function registers - P89LPC9331/9341 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB AD1DAT0 A/D_1 data D5H register 0 AD1DAT1 A/D_1 data D6H register 1 AD1DAT2 A/D_1 data D7H register ...

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Table 4. Special function registers - P89LPC9331/9341 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB DPL Data pointer 82H low FMADRH Program flash E7H address high FMADRL Program flash E6H address low ...

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Table 4. Special function registers - P89LPC9331/9341 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB IEN1* Interrupt E8H EAD enable 1 Bit address BF IP0* Interrupt B8H - priority 0 IP0H Interrupt ...

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Table 4. Special function registers - P89LPC9331/9341 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB P1M1 Port 1 output 91H (P1M1.7) mode 1 P1M2 Port 1 output 92H (P1M2.7) mode 2 P2M1 ...

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Table 4. Special function registers - P89LPC9331/9341 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB SBUF Serial Port data 99H buffer register Bit address 9F SCON* Serial port 98H SM0/FE control SSTAT ...

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Table 4. Special function registers - P89LPC9331/9341 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB WDL Watchdog load C1H WFEED1 Watchdog C2H feed 1 WFEED2 Watchdog C3H feed 2 [1] All ports ...

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Table 5. Extended special function registers - P89LPC9331/9341 Name Description SFR Bit functions and addresses addr. BODCFG BOD FFC8H configuration register CLKCON CLOCK Control FFDEH CLKOK register TPSCON Temperature FFCAH sensor control register RTCDATH Real-time clock FFBFH data register high ...

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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 ACC* Accumulator E0H ADCON0 A/D control 8EH ENBI0 register 0 ADCON1 A/D control 97H ...

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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB AD1DAT3 A/D_1 data F5H register 3 AUXR1 Auxiliary function A2H CLKLP register Bit address ...

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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB DIVM CPU clock 95H divide-by-M control DPTR Data pointer (2 bytes) DPH Data pointer high 83H DPL ...

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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB ICRAH Input capture A ABH register high ICRAL Input capture A AAH register low ICRBH Input capture ...

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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB OCRBL Output compare FAH B register low OCRCH Output compare FDH C register high OCRCL Output compare ...

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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB P3M1 Port 3 output B1H - mode 1 P3M2 Port 3 output B2H - mode 2 PCON ...

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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB SPSTAT SPI status E1H SPIF register SPDAT SPI data register E3H TAMOD Timer 0 and 1 8FH ...

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Table 6. Special function registers - P89LPC9351/9361 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB TPCR2L Prescaler control CAH TPCR2L.7 TPCR2L.6 TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.1 TPCR2L.0 00 register low TRIM Internal ...

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Table 7. Extended special function registers - P89LPC9351/9361 Name Description SFR Bit functions and addresses addr. MSB BODCFG BOD FFC8H configuration register CLKCON CLOCK FFDEH CLKOK Control register PGACON1 PGA1 control FFE1H ENPGA1 register PGACON1B PGA1 control FFE4H register B ...

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... NXP Semiconductors 7.2 Enhanced CPU The P89LPC9331/9341/9351/9361 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 7.3 Clocks 7.3.1 Clock definitions The P89LPC9331/9341/9351/9361 device has several internal clocks as defined below: OSCCLK — ...

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... NXP Semiconductors 7.5 Clock output The P89LPC9331/9341/9351/9361 supports a user-selectable clock output function on the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on XTAL1) and if the RTC and WDT are not using the crystal oscillator as their clock source ...

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... NXP Semiconductors HIGH FREQUENCY XTAL1 MEDIUM FREQUENCY XTAL2 LOW FREQUENCY RC OSCILLATOR WITH CLOCK DOUBLER (7.3728 MHz/14.7456 MHz ± WATCHDOG OSCILLATOR (400 kHz ± Fig 7. Block diagram of oscillator control 7.10 CCLK wake-up delay The P89LPC9331/9341/9351/9361 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used ...

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... NXP Semiconductors 7.13 Memory organization The various P89LPC9331/9341/9351/9361 memory spaces are as follows: • DATA 128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. ...

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... NXP Semiconductors Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority ...

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... NXP Semiconductors RTCF ERTC (RTCCON.1) WDOVF any CCU interrupt (2) EEIF ENADCI0 ADCI0 ENADCI1 ADCI1 ENBI0 BNDI0 ENBI1 BNDI1 (2) EADEE (3) EAD (1) See Section 7.22 “CCU (P89LPC9351/9361)”. (2) P89LPC9351/9361 (3) P89LPC9331/9341 Fig 8. Interrupt sources, interrupt enables, and power-down wake-up sources P89LPC9331_9341_9351_9361 Product data sheet ...

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... NXP Semiconductors 7.16 I/O ports The P89LPC9331/9341/9351/9361 has four I/O ports: Port 0, Port 1, Port 2 and Port 3. Ports 0, 1, and 2 are 8-bit ports, and Port 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 9 ...

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... NXP Semiconductors An open-drain port pin has a Schmitt trigger input that also has a glitch suppression circuit. 7.16.1.3 Input-only configuration The input-only port configuration has no output drivers Schmitt trigger input that also has a glitch suppression circuit. 7.16.1.4 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1 ...

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... NXP Semiconductors 7.17.1 Brownout detection The brownout detect function determines if the power supply voltage drops below a certain level. Enhanced brownout detection has 3 independent functions: BOD reset, BOD interrupt and BOD EEPROM/FLASH. BOD reset is always on except in total Power-down mode. It could not be disabled in software ...

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... NXP Semiconductors Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: Brownout detect, watchdog timer, comparators (note that comparators can be powered down separately), and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled ...

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... NXP Semiconductors 7.19.1 Reset vector Following reset, the P89LPC9331/9341/9351/9361 will fetch instructions from either address 0000H or the Boot address. The Boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00H. The boot address will be used if a UART break reset occurs, or the non-volatile boot status bit (BOOTSTAT ...

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... NXP Semiconductors 7.20.6 Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on ...

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... NXP Semiconductors When a reload occurs, the CCU Timer Overflow Interrupt Flag will be set, and an interrupt generated if enabled. The 16-bit CCU timer may also be used as an 8-bit up/down timer. 7.22.4 Output compare There are four output compare channels and D. Each output compare channel needs to be enabled in order to operate and the user will have to set the associated I/O pin to the desired output mode to connect the pin ...

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... NXP Semiconductors Fig 10. Symmetrical PWM 7.22.7 Alternating output mode In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating pairs for bridge drive control. In this mode the output of these PWM channels are alternately gated on every counter cycle. Fig 11. Alternate output mode 7 ...

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... NXP Semiconductors Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to PCLK/16. 7.22.9 CCU interrupts There are seven interrupt sources on the CCU which share a common interrupt vector. EA (IEN0.7) ECCU (IEN1.4) TOIE2 (TICR2.7) TOIF2 (TIFR2.7) TICIE2A (TICR2.0) TICF2A (TIFR2.0) TICIE2B (TICR2 ...

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... NXP Semiconductors 7.23.2 Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in special function register SCON. The baud rate is variable and is determined by ...

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... NXP Semiconductors 7.23.7 Break detect Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode. 7.23.8 Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SnBUF while the first character is being transmitted ...

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... NXP Semiconductors Fig 14. I P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core 2 I C-bus P1.3/SDA P1.2/SCL P89LPC9331/9341/ 9351/9361 2 C-bus configuration All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 January 2011 OTHER DEVICE OTHER DEVICE 2 2 WITH I ...

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... NXP Semiconductors P1.3/SDA P1.2/SCL Fig 15. I P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core P1.3 INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL status bus I2STAT 2 C-bus serial interface block diagram All information provided in this document is subject to legal disclaimers. Rev. 5 — ...

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... NXP Semiconductors 7.25 SPI The P89LPC9331/9341/9351/9361 provides another high-speed serial communication interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode Mbit/s can be supported in either Master mode or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection ...

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... NXP Semiconductors 7.25.1 Typical SPI configurations Fig 17. SPI single master single slave configuration Fig 18. SPI dual device configuration, where either can be a master or a slave P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core master MISO 8-BIT SHIFT ...

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... NXP Semiconductors Fig 19. SPI single master multiple slaves configuration 7.26 Analog comparators Two analog comparators are provided on the P89LPC9331/9341/9351/9361. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable inputs) is greater than the negative input (selectable from a pin or an internal reference voltage) ...

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... NXP Semiconductors (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF V ref(bg) (P0.2) CIN2A (P0.1) CIN2B Fig 20. Comparator input and output connections (P89LPC9331/9341) (P0.4) CIN1A (P0.3) CIN1B PGA1 (P0.5) CMPREF (P0.2) CIN2A (P0.1) CIN2B Fig 21. Comparator input and output connections (P89LPC9351/9361) 7.26.1 Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used ...

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... NXP Semiconductors 7.26.2 Comparator interrupt Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt ...

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... NXP Semiconductors 7.28 Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler ...

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... NXP Semiconductors 7.29.3 Data EEPROM (P89LPC9351/9361) The P89LPC9351/9361 has 512 bytes of on-chip Data EEPROM. The Data EEPROM is SFR based, byte readable, byte writable, and erasable (via row fill and sector fill). The user can read, write and fill the memory via SFRs and one interrupt. This Data EEPROM provides 100,000 minimum erase/program cycles for each byte. • ...

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... NXP Semiconductors • Programmable security for the code in the flash for each sector. • 100,000 typical erase/program cycles for each byte. • 10 year minimum data retention. 7.30.3 Flash organization The program memory consists of sixteen 1 kB sectors on the P89LPC9361 devices and eight 1 kB sectors on the P89LPC9341/9351 devices and four 1 kB sectors on the P89LPC9331 device ...

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... NXP Semiconductors without additional components. Two methods are available to accomplish IAP. A set of predefined IAP functions are provided in a Boot ROM and can be called through a common interface, PGM_MTP. Several IAP calls are available for use by an application program to permit selective erasing and programming of flash sectors, pages, security bits, configuration bytes, and device ID. These functions are selected by setting up the microcontroller’ ...

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... NXP Semiconductors Table 10. Device P89LPC9341 P89LPC9351 P89LPC9361 7.30.10 Hardware activation of the bootloader The bootloader can also be executed by forcing the device into ISP mode during a power-on sequence (see the P89LPC9331/9341/9351/9361 User manual for specific information). This has the same effect as having a non-zero status byte. This allows an application to be built that will normally execute user code but can be manually forced into ISP operation ...

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... NXP Semiconductors Programmable Gain Amplifier (PGA) with selectable gains of 2x, 4x, 8x, or 16x. (P89LPC9351/9361) On-chip wide range temperature sensor. Four result registers for each A/D. Six operating modes: Fixed channel, single conversion mode. Fixed channel, continuous conversion mode. Auto scan, single conversion mode. ...

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... NXP Semiconductors 8.3 Block diagram AD00 AD01 AD02 AD03 V ref(bg) V sen input MUX AD10 AD11 AD12 AD13 Fig 23. P89LPC9331/9341 ADC block diagram P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core input MUX Anin00 Anin01 Anin02 Anin03 input MUX ...

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... NXP Semiconductors AD00 AD01 AD02 PGA0 AD03 V ref(bg) V sen AD10 AD11 PGA1 AD12 AD13 Fig 24. P89LPC9351/9361 ADC block diagram 8.4 PGA (P89LPC9351/9361) Additional PGA module is integrated in each ADC module to improve the effective resolution of the ADC. A single channel can be selected for amplification. The gain of PGA can be programmable and 16 ...

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... NXP Semiconductors 8.6 ADC operating modes 8.6.1 Fixed channel, single conversion mode A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register pair which corresponds to the selected input channel. An interrupt, if enabled, will be generated after the conversion completes ...

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... NXP Semiconductors in result register, ADxDAT1. The first channel is again converted and its result stored in ADxDAT2. The second channel is again converted and its result placed in ADxDAT3. An interrupt is generated, if enabled, after every set of four conversions (two conversions per channel). In P89LPC9351/9361, in dual channel mode, the PGA channel selection is independent and can be different to A/D conversion channel selection ...

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... NXP Semiconductors An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits. In this case, after the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary high and low registers. If the four MSBs of the conversion meet the interrupt criteria (i ...

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... NXP Semiconductors 9. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter T bias ambient temperature amb(bias) T storage temperature stg I HIGH-level output current per OH(I/O) input/output pin I LOW-level output current per OL(I/O) input/output pin I maximum total input/output current ...

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... NXP Semiconductors 10. Static characteristics Table 12. Static characteristics 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, amb Symbol Parameter I operating supply current DD(oper) I Idle mode supply current DD(idle) I Power-down mode supply DD(pd) current I total Power-down mode DD(tpd) supply current ...

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... NXP Semiconductors Table 12. Static characteristics 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, amb Symbol Parameter I LOW-level input current IL I input leakage current LI I HIGH-LOW transition THL current R internal pull-up resistance RST_N(int) on pin RST V band gap reference voltage ...

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... NXP Semiconductors 10.1 Current characteristics Note: The graphs provided are a statistical summary based on a limited number of samples and only for information purposes. The performance characteristics listed are not tested or guaranteed. (mA) Fig 26. I (mA) Fig 27. I P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core ...

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... NXP Semiconductors (mA) Fig 28. I (mA) Fig 29. I P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core 2.4 2.8 Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock. vs. frequency at +85 °C DD(oper) 5 4.0 3.0 2.0 1.0 ...

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... NXP Semiconductors (mA) Fig 30. I (mA) Fig 31. I P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core 5 4.0 3.0 2.0 1.0 0.0 2.4 2.8 Test conditions: idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. ...

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... NXP Semiconductors (μA) (1) +85 °C (2) +25 °C (3) −40 °C Fig 32. I (μA) (1) +85 °C (2) −40 °C (3) +25 °C Fig 33. I P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core 20 18.0 16.0 14.0 12.0 10.0 2.4 2.8 Test conditions: power-down mode, using internal RC oscillator with the following functions disabled: comparators, real-time clock, and watchdog timer ...

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... NXP Semiconductors 10.2 Internal RC/watchdog oscillator characteristics Note: The graphs provided are a statistical summary based on a limited number of samples and only for information purposes. The performance characteristics listed are not tested or guaranteed. frequency deviation (%) Fig 34. Average internal RC oscillator frequency vs. V frequency ...

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... NXP Semiconductors frequency deviation (%) Fig 36. Average internal RC oscillator frequency vs. V frequency deviation (%) Fig 37. Average watchdog oscillator frequency vs. V P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core 0.2 0 −0.2 −0.4 −0.6 2.4 2.8 Central frequency of internal RC oscillator = 7.3728 MHz 2 ...

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... NXP Semiconductors frequency deviation (%) Fig 38. Average watchdog oscillator frequency vs. V frequency deviation (%) Fig 39. Average watchdog oscillator frequency vs. V P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core 0.5 −0.5 −1.5 −2.5 −3.5 2.4 2.8 Central frequency of watchdog oscillator = 400 KHz 1 ...

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... NXP Semiconductors 10.3 BOD characteristics Table 13. BOD static characteristics 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, amb Symbol Parameter BOD interrupt V trip voltage trip BOD reset V trip voltage trip BOD EEPROM/FLASH V trip voltage trip [1] Typical ratings are not guaranteed. The values listed are at room temperature ...

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... NXP Semiconductors 11. Dynamic characteristics Table 14. Dynamic characteristics (12 MHz 2 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, amb Symbol Parameter f internal RC oscillator osc(RC) frequency f internal watchdog osc(WD) oscillator frequency f oscillator frequency osc T clock cycle time cy(clk) f low-power select clock ...

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... NXP Semiconductors Table 14. Dynamic characteristics (12 MHz 2 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, amb Symbol Parameter T SPI cycle time SPICYC slave master t SPI enable lead time SPILEAD slave t SPI enable lag time SPILAG slave t SPICLK HIGH time ...

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... NXP Semiconductors Table 15. Dynamic characteristics (18 MHz 3 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, amb Symbol Parameter f internal RC oscillator osc(RC) frequency f internal watchdog osc(WD) oscillator frequency f oscillator frequency osc T clock cycle time cy(clk) f low-power select clock CLKLP frequency ...

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... NXP Semiconductors Table 15. Dynamic characteristics (18 MHz 3 3.6 V unless otherwise specified. DD − ° ° +85 C for industrial applications, amb Symbol Parameter t SPI enable lead time SPILEAD slave t SPI enable lag time SPILAG slave t SPICLK HIGH time SPICLKH slave master t SPICLK LOW time ...

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... NXP Semiconductors 11.1 Waveforms Fig 41. External clock timing (with an amplitude of at least V clock t QVXH output data write to SBUF t XHDV input data clear RI Fig 42. Shift register mode timing SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t MOSI SPIF (output) Fig 43. SPI master timing (CPHA = 0) ...

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... NXP Semiconductors SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 44. SPI master timing (CPHA = SPIF t SPILEAD SPICLK (CPOL = 0) (input) t SPICLK (CPOL = 1) (input) t SPIA MISO (output) t SPIDSU MOSI (input) Fig 45. SPI slave timing (CPHA = 0) P89LPC9331_9341_9351_9361 Product data sheet ...

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... NXP Semiconductors SS t SPIF t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIOH t SPIDV t SPIA MISO not defined (output) MOSI (input) Fig 46. SPI slave timing (CPHA = 1) 11.2 ISP entry mode Table 16. Dynamic characteristics, ISP entry mode 3.6 V, unless otherwise specified. ...

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... NXP Semiconductors 12. Other characteristics 12.1 Comparator electrical characteristics Table 17. Comparator electrical characteristics 3.6 V, unless otherwise specified. DD − ° ° +85 C for industrial applications, amb Symbol Parameter V input offset voltage IO V common-mode input voltage IC CMRR common-mode rejection ratio t total response time ...

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... NXP Semiconductors 12.2 ADC/PGA/temperature sensor electrical characteristics Table 18. ADC/PGA/temperature sensor electrical characteristics 3.6 V, unless otherwise specified. DD − ° ° +85 C for industrial applications, amb All limits valid for an external source impedance of less than 10 k Symbol Parameter V analog input voltage IA C analog input capacitance ...

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... NXP Semiconductors start trigger 1 2 adc_clk clk serial_data_out ADCDATA_REG Fig 48. ADC conversion timing P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 January 2011 © NXP B.V. 2011. All rights reserved. ...

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... NXP Semiconductors 255 254 253 252 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. Fig 49. ADC characteristics P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core (2) 1 LSB (ideal (LSB ) IA ideal All information provided in this document is subject to legal disclaimers. ...

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... NXP Semiconductors 13. Package outline PLCC28: plastic leaded chip carrier; 28 leads pin 1 index 4 β DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT min. max. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1 ...

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... NXP Semiconductors TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

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... NXP Semiconductors 14. Abbreviations Table 19. Acronym ADC CPU CCU CRC DAC EPROM EEPROM EMI LSB MSB PGA PLL PWM RAM RC RTC SAR SFR SPI UART WDT P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core Abbreviations Description Analog to Digital Converter ...

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... NXP Semiconductors 15. Revision history Table 20. Revision history Document ID Release date P89LPC9331_9341_9351_ 20110110 9361 v.5 Modifications: P89LPC9331_9341_9351_ 20100910 9361 v.4 P89LPC9331_9341_9351_ 20090602 9361 v.3 P89LPC9331_9341_9351 v.2 20090505 P89LPC9351 v.1 20081119 P89LPC9331_9341_9351_9361 Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core ...

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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

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... Product data sheet P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 12 7.1 Special function registers . . . . . . . . . . . . . . . . 12 7 ...

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... NXP Semiconductors 7.30.1 General description . . . . . . . . . . . . . . . . . . . . 55 7.30.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.30.3 Flash organization . . . . . . . . . . . . . . . . . . . . . 56 7.30.4 Using flash as data storage . . . . . . . . . . . . . . 56 7.30.5 Flash programming and erasing . . . . . . . . . . . 56 7.30.6 ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.30.7 IAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.30.8 ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.30.9 Power-on reset code execution . . . . . . . . . . . 57 7.30.10 Hardware activation of the bootloader . . . . . . 58 7.31 User configuration bytes . . . . . . . . . . . . . . . . . 58 7.32 User sector security bytes ...

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