P89LPC9402FBD,557 NXP Semiconductors, P89LPC9402FBD,557 Datasheet
P89LPC9402FBD,557
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P89LPC9402FBD,557 Summary of contents
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P89LPC9402 8-bit microcontroller with accelerated two-clock 80C51 core byte-erasable flash with 32 segment 4 LCD driver Rev. 01 — 22 April 2009 1. General description The P89LPC9402 is a multi-chip module consisting of a P89LPC931A1 single-chip ...
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... NXP Semiconductors I Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. I Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application. I In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application ...
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... NXP Semiconductors 3. Ordering information Table 1. Type number P89LPC9402FBD 3.1 Ordering options Table 2. Type number P89LPC9402FBD P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Ordering information Package Name Description LQFP64 plastic low profile quad flat package; 64 leads; body 14 ...
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... NXP Semiconductors 4. Block diagram P3[1:0] P2.5, P2[3:0] P1[7:0] P0[7:0] Fig 1. Block diagram P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core P89LPC931A1 MCU Rev. 01 — 22 April 2009 P89LPC9402 S[31:0] BP[3:0] PCF8576D LCD CONTROLLER V LCD 002aae470 © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors P89LPC931A1 P3[1:0] P2.5, P2[3:0] P1[7:0] P0[7:0] XTAL1 CRYSTAL OR RESONATOR XTAL2 Fig 2. Microcontroller section block diagram P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core ACCELERATED 2-CLOCK 80C51 CPU 8 kB CODE FLASH internal bus 256-BYTE DATA RAM PORT 3 ...
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... NXP Semiconductors V DD LCD BIAS GENERATOR V LCD CLK TIMING SYNC OSCILLATOR OSC V SS SCL_LCD INPUT FILTERS SDA_LCD Fig 3. LCD display controller block diagram 5. Functional diagram CLKOUT Fig 4. P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core BP0 BP1 BP2 BP3 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 5. 6.2 Pin description Table 3. Pin description Symbol Pin Type Description P0.0 to P0.7 I/O P0.0/CMP2/ 8 I/O KBI0 O I P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 1 P0.5/CMPREF/KBI5 P0.4/CIN1A/KBI4 2 P0.3/CIN1B/KBI3 3 P0.2/CIN2A/KBI2 4 5 P0.1/CIN2B/KBI1 P2 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type Description P0.1/CIN2B/ 5 I/O KBI1 I I P0.2/CIN2A/ 4 I/O KBI2 I I P0.3/CIN1B/ 3 I/O KBI3 I I P0.4/ CIN1A/ 2 I/O KBI4 I I P0.5/ 1 I/O CMPREF/ I KBI5 I P0.6/CMP1/ 24 I/O KBI6 O I P0.7/T1/KBI7 23 I/O I/O I P1.0 to P1.7 I/O, I [1] P1 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type Description P1.5/RST P1.6 10 I/O P1.7 9 I/O P2.0 to P2.3, I/O P2.5 P2.0 6 I/O P2.1 7 I/O P2.2/MOSI 18 I/O I/O P2.3/MISO 19 I/O I/O P2.5/SPICLK 20 I/O I/O P3.0 to P3.1 I/O P3.0/XTAL2/ 14 I/O CLKOUT O O P3.1/XTAL1 13 I/O ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type Description S0 to S31 LCD [1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5. P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core S0 to S31: LCD segment outputs. Ground reference. Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes ...
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... NXP Semiconductors 7. Functional description Remark: Please refer to the P89LPC9402 User manual for a more detailed functional description. 7.1 Special function registers Remark: Special Function Registers (SFRs) accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. ...
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Table 4. Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H AUXR1 Auxiliary function register A2H Bit address B* B register F0H [1] BRGR0 Baud rate generator rate low BEH ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. I2SCLH Serial clock generator/SCL DDH duty cycle register high I2SCLL Serial clock generator/SCL DCH duty cycle register low 2 I2STAT I C-bus status ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. P0M1 Port 0 output mode 1 84H P0M2 Port 0 output mode 2 85H P1M1 Port 1 output mode 1 91H P1M2 Port ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. TAMOD Timer 0 and 1 auxiliary 8FH mode Bit address TCON* Timer 0 and 1 control 88H TH0 Timer 0 high 8CH TH1 ...
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Table 5. Extended special function registers Name Description SFR Bit functions and addresses addr. BODCFG BOD FFC8H configuration register CLKCON CLOCK Control FFDEH CLKOK register RTCDATH Real-time clock FFBFH data register high RTCDATL Real-time clock FFBEH data register low [1] ...
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... NXP Semiconductors 7.2 Enhanced CPU The P89LPC9402 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 7.3 Clocks 7.3.1 Clock definitions The P89LPC9402 device has several internal clocks as defined below: OSCCLK — ...
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... NXP Semiconductors 7.3.4 Clock output The P89LPC9402 supports a user-selectable clock output function on the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on XTAL1) and if the RTC and WDT are not using the crystal oscillator as their clock source ...
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... NXP Semiconductors HIGH FREQUENCY XTAL1 MEDIUM FREQUENCY XTAL2 LOW FREQUENCY RC OSCILLATOR WITH CLOCK DOUBLER (7.3728 MHz/14.7456 MHz WATCHDOG OSCILLATOR (400 kHz Fig 6. Block diagram of oscillator control - P89LPC9402 P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core OSCCLK RCCLK 1 %) ...
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... NXP Semiconductors 7.8 CPU Clock (CCLK) wake-up delay The P89LPC9402 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 100 s ...
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... NXP Semiconductors • CODE Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC9402 has on-chip Code memory. 7.12 Data RAM arrangement The 768 bytes of on-chip RAM are organized as shown in Table 6. Type DATA IDATA 7.13 Interrupts The P89LPC9402 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources ...
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... NXP Semiconductors RTCF ERTC (RTCCON.1) WDOVF Fig 7. Interrupt sources, interrupt enables, and power-down wake-up sources 7.14 I/O ports The P89LPC9402 has four I/O ports: Port 0 and Port 1 are 8-bit ports. Port 5-bit port. Port 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 7 ...
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... NXP Semiconductors 7.14.1 Port configurations All but three I/O port pins on the P89LPC9402 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open-drain, and input-only. Two configuration registers for each port select the output type for each port pin. 1. P1.5 (RST) can only be an input and cannot be confi ...
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... NXP Semiconductors Digital outputs are disabled by putting the port output into the Input-Only (high-impedance) mode. Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5. On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions. 7.14.3 Additional port features After power-up, all pins are in Input-Only mode ...
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... NXP Semiconductors 7.15.2 Power-on detection The Power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software. ...
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... NXP Semiconductors Note: During a power cycle ensure a power-on reset (see Reset can be triggered from the following sources: • External reset pin (during power- user configured via UCFG1) • Power-on detect • Brownout detect • Watchdog timer • Software reset • ...
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... NXP Semiconductors 7.18.2 Mode 1 Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used. 7.18.3 Mode 2 Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1. 7.18.4 Mode 3 When Timer Mode stopped ...
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... NXP Semiconductors 7.20.2 Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overfl ...
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... NXP Semiconductors 7.20.7 Break detect Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode. 7.20.8 Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the fi ...
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... NXP Semiconductors 2 7.21 I C-bus serial interface 2 The I C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features: • Bidirectional data transfer between masters and slaves • Multi master bus (no central master) • ...
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... NXP Semiconductors P1.3/SDA P1.2/SCL Fig 10. I P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core P1.3 INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL status bus I2STAT 2 C-bus serial interface block diagram Rev. 01 — 22 April 2009 ...
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... NXP Semiconductors 7.22 SPI The P89LPC9402 provides another high-speed serial communication interface, the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode 4.5 Mbit/s can be supported in Master mode Mbit/s in Slave mode. It has a transfer completion flag and write collision fl ...
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... NXP Semiconductors 7.22.1 Typical SPI configurations Fig 12. SPI single master single slave configuration Fig 13. SPI dual device configuration, where either can be a master or a slave P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core master MISO ...
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... NXP Semiconductors Fig 14. SPI single master multiple slaves configuration P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core master MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK port GENERATOR port Rev. 01 — 22 April 2009 P89LPC9402 slave MISO 8-BIT SHIFT ...
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... NXP Semiconductors 7.23 Analog comparators Two analog comparators are provided on the P89LPC9402. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage) ...
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... NXP Semiconductors If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place ...
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... NXP Semiconductors 7.25 Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler ...
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... NXP Semiconductors 7.27 LCD driver 7.27.1 General description The LCD segment driver in the P89LPC9402 can interface to most LCDs using low multiplex rates. It generates the drive signals for static or multiplexed LCDs containing up to four backplanes and segments. The LCD controller communicates to a host using the I LCD driver are available on the P89LPC9402 providing system fl ...
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... NXP Semiconductors 7.27.5 Timing The LCD controller timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency is a fi ...
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... NXP Semiconductors 7.27.12 Input bank selector The input bank selector loads display data into the display RAM based on the selected LCD drive configuration. The BANK SELECT command can be used to load display data in bit 2 in static drive mode or in bits 2 and 3 in 1:2 mode. The input bank selector functions are independent of the output bank selector ...
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... NXP Semiconductors 7.28 Flash program memory 7.28.1 General description The P89LPC9402 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory ...
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... NXP Semiconductors 7.28.5 Flash programming and erasing Four different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IAP) under control of the application’s firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock - serial data interface ...
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... NXP Semiconductors in components and circuit board area. The ISP function uses five pins (V RXD, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature. 7.28.9 Power-on reset code execution The P89LPC9402 contains two special flash elements: the Boot Vector and the Boot Status bit ...
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... NXP Semiconductors 8. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter T bias ambient temperature amb(bias) T storage temperature stg I HIGH-level output current per OH(I/O) input/output pin I LOW-level output current per OL(I/O) input/output pin I maximum total input/output current ...
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... NXP Semiconductors 9. Static characteristics Table 12. Static electrical characteristics 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter I operating supply current DD(oper) I Idle mode supply current DD(idle) I Power-down mode supply DD(pd) current I total Power-down mode supply ...
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... NXP Semiconductors Table 12. Static electrical characteristics 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter V brownout trip voltage bo V band gap reference voltage ref(bg) TC band gap temperature bg coefficient [1] Typical ratings are not guaranteed. The values listed are at room temperature, V ...
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... NXP Semiconductors 10. Dynamic characteristics Table 13. Dynamic characteristics (12 MHz 2 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter f internal RC oscillator frequency osc(RC) f internal watchdog oscillator osc(WD) frequency f oscillator frequency osc T clock cycle time cy(clk) f low-power select clock frequency CLKLP Glitch fi ...
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... NXP Semiconductors Table 13. Dynamic characteristics (12 MHz 2 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter t SPI enable lag time SPILAG slave t SPICLK HIGH time SPICLKH master slave t SPICLK LOW time SPICLKL master slave t SPI data set-up time ...
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... NXP Semiconductors Table 14. Dynamic characteristics (18 MHz 3 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter f internal RC oscillator frequency osc(RC) f internal watchdog oscillator frequency osc(WD) f oscillator frequency osc T clock cycle time cy(clk) f low-power select clock frequency CLKLP Glitch fi ...
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... NXP Semiconductors Table 14. Dynamic characteristics (18 MHz 3 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter t SPICLK HIGH time SPICLKH master slave t SPICLK LOW time SPICLKL master slave t SPI data set-up time SPIDSU master or slave ...
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... NXP Semiconductors 10.1 Waveforms clock t QVXH output data write to SBUF t XHDV input data clear RI Fig 17. Shift register mode timing Fig 18. External clock timing (with an amplitude of at least V SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t MOSI SPIF (output) Fig 19. SPI master timing (CPHA = 0) ...
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... NXP Semiconductors SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 20. SPI master timing (CPHA = SPIR t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIA MISO (output) t SPIDSU MOSI (input) Fig 21. SPI slave timing (CPHA = 0) P89LPC9402_1 Product data sheet ...
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... NXP Semiconductors SS t SPIR t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIOH t SPIDV t SPIA MISO not defined (output) MOSI (input) Fig 22. SPI slave timing (CPHA = 1) 10.2 ISP entry mode Table 15. Dynamic characteristics, ISP entry mode 3.6 V, unless otherwise specified. ...
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... NXP Semiconductors 11. Other characteristics 11.1 Comparator electrical characteristics Table 16. Comparator electrical characteristics 3.6 V, unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter V input offset voltage IO V common-mode input voltage IC CMRR common-mode rejection ratio t total response time ...
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... NXP Semiconductors 12. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors 13. Abbreviations Table 17. Acronym BOD CPU EPROM EMI LCD LED PWM RAM RC RTC SFR SPI UART WDT P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Acronym list Description Brownout Detect Central Processing Unit Erasable Programmable Read-Only Memory ...
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... NXP Semiconductors 14. Revision history Table 18. Revision history Document ID Release date P89LPC9402_1 20090422 P89LPC9402_1 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Data sheet status Change notice Product data sheet - Rev. 01 — 22 April 2009 P89LPC9402 Doc. number Supersedes - - © NXP B.V. 2009. All rights reserved. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 6 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . 11 7.1 Special function registers . . . . . . . . . . . . . . . . 11 7.2 Enhanced CPU ...
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... NXP Semiconductors 7.27.11 Output bank selector 7.27.12 Input bank selector . . . . . . . . . . . . . . . . . . . . . 40 7.27.13 Blinker 7.27.13.1 I C-bus controller . . . . . . . . . . . . . . . . . . . . . . 40 7.27.14 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2 7.27.15 I C-bus slave addresses . . . . . . . . . . . . . . . . . 40 7.28 Flash program memory 7.28.1 General description 7.28.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.28.3 Flash organization . . . . . . . . . . . . . . . . . . . . . 41 7.28.4 Using flash as data storage . . . . . . . . . . . . . . 41 7.28.5 Flash programming and erasing ...