LPC2103FBD48,118 NXP Semiconductors, LPC2103FBD48,118 Datasheet - Page 14

IC ARM7 MCU FLASH 32K 48-LQFP

LPC2103FBD48,118

Manufacturer Part Number
LPC2103FBD48,118
Description
IC ARM7 MCU FLASH 32K 48-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2100r
Datasheet

Specifications of LPC2103FBD48,118

Core Processor
ARM7
Core Size
16/32-Bit
Speed
70MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
LPC21
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, JTAG, SPI, SSP, UART
Maximum Clock Frequency
70 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DB-LQFP48-LPC2103, MCB2103, MCB2103U, MCB2103UME, KSK-LPC2103-01, KSK-LPC2103-01PL, KSK-LPC2103-02
Development Tools By Supplier
OM10079, OM10081, OM10090
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
568-4302 - BOARD EVAL LPC210X KS2103 JLINK568-4301 - BOARD EVAL LPC210X KS2103568-4300 - BOARD EVAL LPC210X MCB2103568-4297 - BOARD EVAL LPC21XX MCB2100MCB2103UME - BOARD EVAL MCB2103 + ULINK-MEMCB2103U - BOARD EVAL MCB2103 + ULINK2622-1013 - BOARD FOR LPC2103 48-LQFP622-1008 - BOARD FOR LPC9103 10-HVSONMCB2103 - BOARD EVAL NXP LPC2101/2101/2103
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
935280966118
LPC2103FBD48-T
LPC2103FBD48-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC2103FBD48,118
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC2101_02_03_4
Product data sheet
6.10.1 Features
6.11.1 Features
6.10 I
6.11 SPI serial I/O controller
The LPC2101/02/03 each contain two I
The I
(SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., LCD driver) or a transmitter with the
capability to both receive and send information such as serial memory. Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I
it can be controlled by more than one bus master connected to it.
The I
I
The LPC2101/02/03 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the
slave, and the slave always sends 8 bits to 16 bits of data to the master.
2
2
C-bus).
C-bus serial I/O controllers
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
UART1 is equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
Compliant with standard I
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
Compliant with SPI specification.
Synchronous, Serial, Full Duplex, Communication.
2
2
C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line
C-bus implemented in LPC2101/02/03 supports bit rates up to 400 kbit/s (Fast
2
C-bus can also be used for test and diagnostic purposes.
Rev. 04 — 2 June 2009
2
C-bus interface.
2
C-bus controllers.
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
2
C-bus is a multi-master bus,
© NXP B.V. 2009. All rights reserved.
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