P89LV51RD2FA,512 NXP Semiconductors, P89LV51RD2FA,512 Datasheet

IC 80C51 MCU 1024 RAM 44PLCC

P89LV51RD2FA,512

Manufacturer Part Number
P89LV51RD2FA,512
Description
IC 80C51 MCU 1024 RAM 44PLCC
Manufacturer
NXP Semiconductors
Series
89LVr
Datasheet

Specifications of P89LV51RD2FA,512

Core Processor
8051
Core Size
8-Bit
Speed
33MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
P89LV5x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, UART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Package
44PLCC
Device Core
80C51
Family Name
89LV
Maximum Speed
40 MHz
For Use With
622-1017 - BOARD 44-ZIF PLCC SOCKET622-1008 - BOARD FOR LPC9103 10-HVSON
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
935274176512
P89LV51RD2FA
P89LV51RD2FA

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
P89LV51RD2FA,512
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
P89LV51RD2FA,512
Manufacturer:
NXP USA Inc.
Quantity:
422
1. General description
2. Features
The P89LV51RB2/RC2/RD2 are 80C51 microcontrollers with 16/32/64 kB flash and
1024 B of data RAM.
A key feature of the P89LV51RB2/RC2/RD2 is its X2 mode option. The design engineer
can choose to run the application with the conventional 80C51 clock rate (12 clocks per
machine cycle) or select the X2 mode (six clocks per machine cycle) to achieve twice the
throughput at the same clock frequency. Another way to benefit from this feature is to keep
the same performance by reducing the clock frequency by half, thus dramatically reducing
the EMI.
The flash program memory supports both parallel programming and in serial ISP. Parallel
programming mode offers gang-programming at high speed, reducing programming costs
and time to market. ISP allows a device to be reprogrammed in the end product under
software control. The capability to field/update the application firmware makes a wide
range of applications possible.
The P89LV51RB2/RC2/RD2 is also capable of IAP, allowing the flash program memory to
be reconfigured even while the application is running.
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P89LV51RB2/RC2/RD2
8-bit 80C51 3 V low power 16/32/64 kB flash microcontroller
with 1 kB RAM
Rev. 05 — 15 December 2009
80C51 CPU
3 V operating voltage from 0 MHz to 33 MHz
16/32/64 kB of on-chip flash user code memory with ISP and IAP
Supports 12-clock (default) or 6-clock mode selection via software or ISP
SPI and enhanced UART
PCA with PWM and capture/compare functions
Four 8-bit I/O ports with three high-current port 1 pins (16 mA each)
Three 16-bit timers/counters
Programmable watchdog timer
Eight interrupt sources with four priority levels
Second DPTR register
Low EMI mode (ALE inhibit)
TTL- and CMOS-compatible logic levels
Product data sheet

Related parts for P89LV51RD2FA,512

P89LV51RD2FA,512 Summary of contents

Page 1

P89LV51RB2/RC2/RD2 8-bit 80C51 3 V low power 16/32/64 kB flash microcontroller with 1 kB RAM Rev. 05 — 15 December 2009 1. General description The P89LV51RB2/RC2/RD2 are 80C51 microcontrollers with 16/32/64 kB flash and 1024 B of data RAM. A ...

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... NXP Semiconductors I Brownout detection I Low power modes N Power-down mode with external interrupt wake-up N Idle mode I PLCC44 and TQFP44 packages 3. Ordering information Table 1. Ordering information Type number Package Name P89LV51RB2BA PLCC44 P89LV51RC2FBC TQFP44 P89LV51RD2FA PLCC44 P89LV51RD2BBC TQFP44 3.1 Ordering options Table 2. Type number ...

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... NXP Semiconductors 4. Block diagram P89LV51RB2/RC2/RD2 P3[7:0] P2[7:0] P1[7:0] P0[7:0] XTAL1 CRYSTAL OR RESONATOR XTAL2 Fig 1. Block diagram P89LV51RB2_RC2_RD2_5 Product data sheet P89LV51RB2/RC2/RD2 HIGH PERFORMANCE 80C51 CPU 16/32/64 kB CODE FLASH internal bus 1 kB DATA RAM PORT 3 PORT 2 PORT 1 PORT 0 OSCILLATOR Rev. 05 — 15 December 2009 ...

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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. P89LV51RB2_RC2_RD2_5 Product data sheet P1.5/MOSI/CEX2 7 8 P1.6/MISO/CEX3 P1.7/SPICLK/CEX4 9 RST 10 P3.0/RXD 11 12 n.c. P3.1/TXD 13 P3.2/INT0 14 15 P3.3/INT1 16 P3.4/T0 P3.5/T1 17 PLCC44 pin configuration Rev. 05 — 15 December 2009 P89LV51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core 39 P0.4/AD4 38 P0.5/AD5 37 P0 ...

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... NXP Semiconductors Fig 3. P89LV51RB2_RC2_RD2_5 Product data sheet 1 P1.5/MOSI/CEX2 P1.6/MISO/CEX3 2 P1.7/SPICLK/CEX4 3 RST 4 5 P3.0/RXD P89LV51RC2FBC n.c. 6 P89LV51RD2BBC P3.1/TXD 7 8 P3.2/INT0 9 P3.3/INT1 P3.4/T0 10 P3.5/T1 11 TQFP44 pin configuration Rev. 05 — 15 December 2009 P89LV51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core 33 P0.4/AD4 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 ...

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... NXP Semiconductors 5.2 Pin description Table 3. P89LV51RB2/RC2/RD2 pin description Symbol Pin TQFP44 PLCC44 P0.0 to P0.7 P0.0/AD0 37 43 P0.1/AD1 36 42 P0.2/AD2 35 41 P0.3/AD3 34 40 P0.4/AD4 33 39 P0.5/AD5 32 38 P0.6/AD6 31 37 P0.7/AD7 30 36 P1.0 to P1.7 P1.0/ P1.1/T2EX 41 3 P1.2/ECI 42 4 P89LV51RB2_RC2_RD2_5 Product data sheet ...

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... NXP Semiconductors Table 3. P89LV51RB2/RC2/RD2 pin description Symbol Pin TQFP44 PLCC44 P1.3/CEX0 43 5 P1.4/SS/CEX1 44 6 P1.5/MOSI CEX2 P1.6/MISO CEX3 P1.7/SPICLK CEX4 P2.0 to P2.7 P2.0/ P2.1/ P2.2/A10 20 26 P2.3/A11 21 27 P2.4/A12 22 28 P2.5/A13 23 29 P2.6/A14 24 30 P89LV51RB2_RC2_RD2_5 Product data sheet P89LV51RB2/RC2/RD2 …continued Type ...

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... NXP Semiconductors Table 3. P89LV51RB2/RC2/RD2 pin description Symbol Pin TQFP44 PLCC44 P2.7/A15 25 31 P3.0 to P3.7 P3.0/RXD 5 11 P3.1/TXD 7 13 P3.2/INT0 8 14 P3.3/INT1 9 15 P3.4/ P3.5/ P3.6/ P3.7/ PSEN 26 32 RST P89LV51RB2_RC2_RD2_5 Product data sheet P89LV51RB2/RC2/RD2 …continued Type Description I/O P2.7 — Port 2 bit 7. ...

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... NXP Semiconductors Table 3. P89LV51RB2/RC2/RD2 pin description Symbol Pin TQFP44 PLCC44 ALE/PROG 27 33 n.c. 6, 17, 28, 1, 12, 23 XTAL1 15 21 XTAL2 [1] ALE loading issue: When ALE pin experiences higher loading (> 30 pF) during the reset, the microcontroller may accidentally enter into modes other than normal working mode. The solution is to connect a pull-up resistor from pin ALE to V ...

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... NXP Semiconductors 6. Functional description 6.1 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. ...

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Table 4. Special function registers * Indicates SFRs that are bit addressable. Name Description Bit address ACC* Accumulator AUXR Auxiliary function register AUXR1 Auxiliary function register 1 Bit address B* B register CCAP0H Module 0 Capture HIGH CCAP1H Module 1 ...

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Table 4. Special function registers …continued * Indicates SFRs that are bit addressable. Name Description FST Flash Status Register Bit address IEN0* Interrupt Enable 0 Bit address IEN1* Interrupt Enable 1 Bit address IP0* Interrupt Priority IP0H Interrupt Priority 0 ...

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Table 4. Special function registers …continued * Indicates SFRs that are bit addressable. Name Description SADDR Serial Port Address Register SADEN Serial Port Address Enable Bit address SPCTL SPI Control Register SPCFG SPI Configuration Register SPDAT SPI Data SP Stack ...

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... NXP Semiconductors 6.2 Memory organization The device has separate address spaces for program and data memory. 6.2.1 Flash program memory bank selection There are two internal flash memory blocks in the device. Block 0 has 16/32/64 kB and is organized as 128/256/512 sectors, each sector consists of 128 B. Block 1 contains the IAP/ISP routines and may be enabled such that it overlays the fi ...

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... NXP Semiconductors work during initial power up, before the voltage reaches the brownout detection level. The POF flag in the PCON register is set to indicate an initial power up condition. The POF flag will remain active until cleared by software. Following a power-on or external reset the P89LV51RB2/RC2/RD2 will force the SWR and BSEL bits (FCF[1:0 ...

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... NXP Semiconductors V must stay below V DD detection circuit will respond. Brownout interrupt can be enabled by setting the EBO bit (IEN1.3). If EBO bit is set and a brownout condition occurs, a brownout interrupt will be generated to execute the program at location 004BH required that the EBO bit is cleared by software after the brownout interrupt is serviced ...

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... NXP Semiconductors Since the upper 128 B occupy the same addresses as the SFRs, the RAM must be accessed indirectly. The RAM and SFRs space are physically separate even though they have the same addresses. Table 7. Not bit addressable; reset value 00H. Bit Symbol Table 8 ...

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... NXP Semiconductors DPTR points to 0A0H and data in ‘A’ is written to address 0A0H of the expanded RAM rather than external memory. Access to external memory higher than 2FFH using the MOVX instruction will access external memory (0300H to FFFFH) and will perform in the same way as the standard 8051, with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals ...

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... NXP Semiconductors 2FFH 000H Fig 5. 6.2.8 Dual data pointers The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is selected; when DPS = pointers can be accomplished by a single INC instruction on AUXR1 (see ...

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... NXP Semiconductors Fig 6. Dual data pointer organization Table 10. Not bit addressable; reset value 00H. Bit Symbol Table 11. Bit 6.3 Flash memory IAP 6.3.1 Flash organization The P89LV51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block. ISP capability second 8 kB block, is provided to allow the user code to be programmed in-circuit through the serial port. There are three methods of erasing or programming of the fl ...

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... NXP Semiconductors A chip-erase operation can be performed using a commercially available parallel programer. This operation will erase the contents of this boot block and it will be necessary for the user to reprogram this boot block (block 1) with the NXP-provided ISP/IAP code in order to use the ISP or IAP capabilities of this device http://www ...

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... NXP Semiconductors Table 12. Record type P89LV51RB2_RC2_RD2_5 Product data sheet ISP hex record formats Command/data function Program User Code Memory :nnaaaa00dd..ddcc Where number of bytes to program aaaa = address dd..dd = data bytes cc = checksum Example: :100000000102030405006070809cc End of File (EOF), no operation :xxxxxx01cc Where: xxxxxx = required field but value is a ‘don’t care’ ...

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... NXP Semiconductors Table 12. Record type 03 04 P89LV51RB2_RC2_RD2_5 Product data sheet ISP hex record formats …continued Command/data function Miscellaneous Write functions :nnxxxx03ffssddcc Where number of bytes in the record xxxx = required field but value is a ‘don’t care’ subfunction code ss = selection code dd = data (if needed) ...

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... NXP Semiconductors Table 12. Record type P89LV51RB2_RC2_RD2_5 Product data sheet ISP hex record formats …continued Command/data function Miscellaneous Read functions :02xxxx05ffsscc Where number of bytes in the record xxxx = required field but value is a ‘don’t care’ function code for misc read ffss = subfunction and selection code ...

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... NXP Semiconductors Table 12. Record type 6.3.5 Using the serial number This device has the option of storing serial number along with the length of the serial number (for a total non-volatile memory space. When ISP mode is entered, the serial number length is evaluated to determine if the serial number is in use. ...

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... NXP Semiconductors Table 13. IAP function Read ID Erase block 0 Program User Code Read User Code Program Security Bit, Double Clock P89LV51RB2_RC2_RD2_5 Product data sheet IAP function calls IAP call parameters Input parameters 00H DPH = 00H DPL = 00H = mfgr id DPL = 01H = device id 1 DPL = 02H = boot code version number ...

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... NXP Semiconductors Table 13. IAP function Read Security Bit, Double Clock, SoftICE Read Security Bit, Double Clock, SoftICE Erase sector 6.4 Timers/counters 0 and 1 The two 16-bit Timer/counter registers: Timer 0 and Timer 1 can be configured to operate either as timers or event counters (see In the ‘Timer’ function, the register is incremented every machine cycle. Thus, one can think counting machine cycles ...

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... NXP Semiconductors Table 15. Bit Table 16 Table 17. Bit addressable; reset value: 0000 0000B; reset source(s): any reset. Bit Symbol Table 18. Bit P89LV51RB2_RC2_RD2_5 Product data sheet TMOD - Timer/counter mode control register (address 89H) bit descriptions Symbol Description T1/T0 Bits controlling Timer1/Timer0 GATE Gating control when set. Timer/counter ‘x’ is enabled only while ‘INTx’ ...

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... NXP Semiconductors Table 18. Bit 6.4.1 Mode 0 Putting either Timer into mode 0 makes it look like an 8048 Timer, which is an 8-bit counter with a fixed divide-by-32 prescaler. osc/6 Tn pin TnGate INTn pin Fig 7. Timer/counter mode 0 (13-bit counter) In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt fl ...

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... NXP Semiconductors osc/6 Tn pin TRn TnGate INTn pin Fig 8. Timer/counter mode 1 (16-bit counter) 6.4.3 Mode 2 Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1. ...

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... NXP Semiconductors TnGate INT0 pin Fig 10. Timer/counter 0 mode 3 (two 8-bit counters) 6.5 Timer 2 Timer 16-bit Timer/counter which can operate as either an event timer or an event counter, as selected by C/T2 in the special function register T2CON. Timer 2 has four operating modes: Capture, Auto-reload (up or down counting), Clock-out, and Baud Rate ...

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... NXP Semiconductors Table 21. Bit Table 22. Not bit addressable; Reset value: XX00 0000B. Bit Symbol Table 23. Bit 6.5.1 Capture mode In the Capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 16-bit timer or counter (as selected by C/T2 in T2CON) which upon overfl ...

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... NXP Semiconductors OSC 6 T2 pin transition detector T2EX pin Fig 11. Timer 2 in Capture mode This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IEN0 register). If EXEN2 = 1, Timer 2 operates as described above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2 captured into registers RCAP2L and RCAP2H, respectively ...

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... NXP Semiconductors OSC 6 T2 pin transition detector T2EX pin Fig 12. Timer 2 in auto-reload mode (DCEN = 0) In this mode, there are two options selected by bit EXEN2 in T2CON register. If EXEN2 = 0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overfl ...

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... NXP Semiconductors OSC pin Fig 13. Timer 2 in Auto Reload mode (DCEN = 1) A logic 0 applied at pin T2EX causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The external fl ...

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... NXP Semiconductors TCLK = 1, Timer 2 is used as the UART transmit baud rate generator. RCLK has the same effect for the UART receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates – Timer 1 or Timer 2. ...

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... NXP Semiconductors not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Therefore when Timer use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed. When Timer the baud rate generator mode, one should not try to read or write TH2 and TL2. Under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors ...

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... NXP Semiconductors 6.6.2 Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8 data bits (LSB first), and a stop bit (logical 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 6 ...

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... NXP Semiconductors Table 26. Bit Table 27. SM0, SM1 6.6.5 Framing error Framing error (FE) is reported in the SCON.7 bit if SMOD0 (PCON. SMOD0 = 0, SCON.7 is the SM0 bit for the UART recommended that SM0 is set up before SMOD0 is set to ‘1’. 6.6.6 More about UART mode 1 Reception is initiated by a detected 1-to-0 transition at RXD ...

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... NXP Semiconductors The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: ( and (b) either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the fi ...

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... NXP Semiconductors rx_byte(7) saddr(7) rx_byte(0) saddr(0) saddr(7) saden(7) saddr(0) saden(0) Fig 15. Schemes used by the UART to detect ‘given’ and ‘broadcast’ addresses when multiprocessor communications is enabled The following examples help to show the versatility of this scheme. Example 1, slave 0: SADDR = 1100 0000 SADEN = 1111 1101 ...

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... NXP Semiconductors In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Example 1, slave 0: SADDR = 1100 0000 SADEN = 1111 1001 --------------------------------------------------- - Given = 1100 0XX0 Example 2, slave 1: SADDR = 1110 0000 SADEN = 1111 1010 --------------------------------------------------- - Given = 1110 0X0X Example 3, slave 2: SADDR = 1100 0000 ...

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... NXP Semiconductors and slave SPI devices. The SPICLK pin is the clock output and input for the master and slave modes, respectively. The SPI clock generator will start following a write to the master devices SPI data register. The written data is then shifted out of the MOSI pin on the master device into the MOSI pin of the slave device. Following a complete transmission of one byte of data, the SPI clock generator is stopped and the SPIF fl ...

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... NXP Semiconductors Table 29. Bit Table 30. PSC1 Table 31. Bit addressable; reset source(s): any reset; reset value: 0000 0000B. Bit Symbol Table 32. Bit SPICLK cycle # (for reference) SPICLK (CPOL = 0) SPICLK (CPOL = 1) MOSI (from master) MISO (from slave) SS (to slave) Fig 17. SPI transfer format with CPHA = 0 ...

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... NXP Semiconductors S PICL K cycle # (for reference) S PICL K (CPOL = 0) S PICL K (CPOL = 1) MOSI (from master) MISO (from slave) SS (to slave) Fig 18. SPI transfer format with CPHA = 1 6.8 Watchdog timer The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software deadlock and automatic recovery. ...

Page 46

... NXP Semiconductors Table 33. Bit addressable; reset value: 00H. Bit Symbol Table 34. Bit 6.9 PCA The PCA includes a special 16-bit Timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or PWM. ...

Page 47

... NXP Semiconductors In the CMOD SFR there are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during Idle mode, WDTE which enables or disables the Watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overfl ...

Page 48

... NXP Semiconductors PCA TIMER/COUNTER MODULE0 MODULE1 MODULE2 MODULE3 MODULE4 CMOD.0 ECF Fig 21. PCA interrupt system Table 35. Not bit addressable; reset value: 00H. Bit Symbol Table 36. Bit P89LV51RB2_RC2_RD2_5 Product data sheet CCAPMn.0 ECCFn CMOD - PCA counter mode register (address D9H) bit allocation ...

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... NXP Semiconductors Table 37. CPS1 Table 38. Bit addressable; reset value: 00H. Bit Symbol Table 39. Bit Table 40. Not bit addressable; reset value: 00H. Bit Symbol Table 41. Bit P89LV51RB2_RC2_RD2_5 Product data sheet CMOD - PCA counter mode register (address D9H) count pulse select CPS0 Select PCA input ...

Page 50

... NXP Semiconductors Table 41. Bit Table 42. PCA module modes (CCAPMn register) ECOMn CAPPn CAPNn 6.9.1 PCA capture mode To use one of the PCA modules in the capture mode CCAPM bits CAPNn and CAPPn for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’ ...

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... NXP Semiconductors CF CR CEXn - ECOMn 0 Fig 22. PCA capture mode If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. 6.9.2 16-bit software timer mode The PCA modules can be used as software timers and MATn bits in the modules CCAPMn register. The PCA timer will be compared to the module’ ...

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... NXP Semiconductors write to CCAPnH reset write to CCAPnL enable 0 1 Fig 23. PCA compare mode 6.9.3 High-speed output mode In this mode toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOGn, MATn, and ECOMn bits in the module’s CCAPMn SFR must be set ...

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... NXP Semiconductors write to reset CCAPnH write to CCAPnL enable 0 1 Fig 24. PCA high-speed output mode 6.9.4 PWM mode All of the PCA modules can be used as PWM outputs depends on the source for the PCA timer. enable - ECOMn CAPPn 1 Fig 25. PCA PWM mode All of the modules will have the same frequency of output because they all share only one PCA timer. The duty cycle of each module is independently variable using the module’ ...

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... NXP Semiconductors module’s CCAPnL SFR the output will be LOW, when it is equal to or greater than, the output will be HIGH. When CL overflows from FF to 00, CCAPnL is reloaded with the value in CCAPnH. This allows updating the PWM without glitches. The PWMn and ECOMn bits in the module’ ...

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... NXP Semiconductors 6.10 Security bit The Security Bit protects against software piracy and prevents the contents of the flash from being read by unauthorized parties in Parallel Programmer mode. It also protects against code corruption resulting from accidental erasing and programming to the internal flash memory. ...

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... NXP Semiconductors 0 INT0# IT0 1 brownout TF0 0 INT1# IT1 1 TF1 ECF CF CCFn ECCFn RI TI SPIF SPIE TF2 EXF2 Fig 26. Interrupt structure Table 44. Bit addressable; reset value: 00H. Bit Symbol P89LV51RB2_RC2_RD2_5 Product data sheet IP/IPH/IPA/IPAH IE and IEA registers IE0 IE1 global individual disable ...

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... NXP Semiconductors Table 45. Bit Table 46. Bit addressable; reset value: 00H. Bit Symbol Table 47. Bit Table 48. Bit addressable; reset value: 00H. Bit Symbol Table 49. Bit Table 50. Not bit addressable; reset value: 00H. Bit Symbol P89LV51RB2_RC2_RD2_5 Product data sheet IEN0 - Interrupt enable register 0 (address A8H) bit descriptions ...

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... NXP Semiconductors Table 51. Bit Table 52. Bit addressable; reset value: 00H. Bit Symbol Table 53. Bit Table 54. Not bit addressable; reset value: 00H. Bit Symbol Table 55. Bit 6.12 Power-saving modes The device provides two power saving modes of operation for applications where power consumption is critical. The two modes are Idle and Power-down, see 6 ...

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... NXP Semiconductors The device exits Idle mode through either a system interrupt or a hardware reset. When exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits Idle mode. After exiting the Interrupt Service Routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the Idle mode ...

Page 60

... NXP Semiconductors 6.13 System clock and clock options 6.13.1 Clock input options and recommended capacitor values for oscillator Shown in amplifier, which can be configured for use as an on-chip oscillator. When driving the device from an external clock source, XTAL2 should be left disconnected and XTAL1 should be driven ...

Page 61

... NXP Semiconductors Table 58. Device P89LV51RB2/RC2/RD2 12 Table 59. Not Bit addressable; reset value: xxxx x0xxB. Bit Symbol Table 60. Bit P89LV51RB2_RC2_RD2_5 Product data sheet Clock doubling features Standard mode (X1) Clocks per Maximum machine cycle external clock frequency (MHz) 33 FST - Flash status register (address B6) bit allocation ...

Page 62

... NXP Semiconductors 7. Limiting values Table 61. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted. Symbol Parameter T bias ambient temperature amb(bias) ...

Page 63

... NXP Semiconductors Table 62. Static characteristics + + amb Symbol Parameter V HIGH-level output voltage OH V brownout trip voltage bo I LOW-level input current IL I HIGH-LOW transition current THL I input leakage current LI R pull-down resistance pd C input capacitance iss I operating supply current DD(oper) I Idle mode supply current ...

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... NXP Semiconductors (mA (1) Maximum I DD(oper) (2) Maximum I DD(idle) (3) Typical I DD(oper) (4) Typical I DD(idle) Fig 28. Supply current versus frequency P89LV51RB2_RC2_RD2_5 Product data sheet Rev. 05 — 15 December 2009 P89LV51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core 001aak852 (1) (2) (3) ( internal clock frequency (MHz) © NXP B.V. 2009. All rights reserved. ...

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... NXP Semiconductors 9. Dynamic characteristics Table 63. Dynamic characteristics Over operating conditions: load capacitance for Port 0, ALE, and PSEN = 100 pF; load capacitance for all other outputs = amb Symbol Parameter f oscillator frequency osc t ALE pulse width LHLL t address valid to ALE LOW time AVLL ...

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... NXP Semiconductors 9.1 Explanation of symbols Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The characters are described below: A — ...

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... NXP Semiconductors ALE PSEN RD t LLAX t AVLL port 0 from RI to DPL port 2 Fig 30. External data memory read cycle t LHLL ALE PSEN WR t AVLL from RI or DPL port 0 port 2 Fig 31. External data memory write cycle P89LV51RB2_RC2_RD2_5 Product data sheet t LLDV t t LLWL ...

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... NXP Semiconductors Table 64. External clock drive Symbol Parameter f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time CLCH t clock fall time CHCL Fig 32. External clock drive waveform Table 65. Serial port timing Symbol ...

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... NXP Semiconductors instruction ALE clock t QVXH output data write to SBUF t XHDV input data clear RI Fig 33. Shift register mode timing waveforms Fig 34. Test load example All other pins disconnected Fig 35. I test condition, Active mode DD P89LV51RB2_RC2_RD2_5 Product data sheet T XLXL t XHQX XHDX ...

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... NXP Semiconductors All other pins disconnected Fig 36. I test condition, Idle mode DD All other pins disconnected Fig 37. I test condition, Power-down mode DD P89LV51RB2_RC2_RD2_5 Product data sheet P89LV51RB2/RC2/RD2 RST EA DUT (n.c.) XTAL2 clock XTAL1 signal V SS 002aaa557 RST EA DUT XTAL2 (n.c.) XTAL1 ...

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... NXP Semiconductors 10. Package outline PLCC44: plastic leaded chip carrier; 44 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

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... NXP Semiconductors TQFP44: plastic thin quad flat package; 44 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.05 1.2 mm 0.25 0.05 0.95 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT376-1 137E08 Fig 39 ...

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... NXP Semiconductors 11. Abbreviations Table 66. Acronym DUT EMI IAP ISP MCU PCA PWM RC SFR SPI TTL UART P89LV51RB2_RC2_RD2_5 Product data sheet Abbreviations Description Device Under Test Electro-Magnetic Interference In-Application Programming In-System Programming Microcontroller Unit Programmable Counter Array Pulse Width Modulator Resistance-Capacitance Special Function Register ...

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... Data sheet status Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 3: Removed sentence “However, Security lock level 4 will disable EA...” for EA description ...

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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . 10 6.1 Special function registers . . . . . . . . . . . . . . . . 10 6.2 Memory organization . . . . . . . . . . . . . . . . . . . 14 6.2.1 Flash program memory bank selection 6.2.2 Power-on reset code execution ...

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