P89LV51RD2FA,512 NXP Semiconductors, P89LV51RD2FA,512 Datasheet - Page 20

IC 80C51 MCU 1024 RAM 44PLCC

P89LV51RD2FA,512

Manufacturer Part Number
P89LV51RD2FA,512
Description
IC 80C51 MCU 1024 RAM 44PLCC
Manufacturer
NXP Semiconductors
Series
89LVr
Datasheet

Specifications of P89LV51RD2FA,512

Core Processor
8051
Core Size
8-Bit
Speed
33MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
P89LV5x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, UART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Package
44PLCC
Device Core
80C51
Family Name
89LV
Maximum Speed
40 MHz
For Use With
622-1017 - BOARD 44-ZIF PLCC SOCKET622-1008 - BOARD FOR LPC9103 10-HVSON
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
935274176512
P89LV51RD2FA
P89LV51RD2FA

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
P89LV51RD2FA,512
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
P89LV51RD2FA,512
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
P89LV51RB2_RC2_RD2_5
Product data sheet
6.3.1 Flash organization
6.3.2 Boot block (block 1)
6.3 Flash memory IAP
Table 10.
Not bit addressable; reset value 00H.
Table 11.
The P89LV51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block. ISP
capability, in a second 8 kB block, is provided to allow the user code to be programmed
in-circuit through the serial port. There are three methods of erasing or programming of
the flash memory that may be used. First, the flash may be programmed or erased in the
end-user application by calling low-level routines through a common entry point (IAP).
Second, the on-chip ISP bootloader may be invoked. This ISP bootloader will, in turn, call
low-level routines through the same common entry point that can be used by the end-user
application. Third, the flash may be programmed or erased using the parallel method by
using a commercially available EPROM programmer which supports this device.
When the microcontroller programs its own flash memory, all of the low level details are
handled by code that is contained in block 1. A user program calls the common entry point
in the block 1 with appropriate parameters to accomplish the desired operation. Boot block
operations include erase user code, program user code, program security bits, etc.
Bit
7 to 4
3
2
1
0
Bit
Symbol
Fig 6. Dual data pointer organization
AUXR1 - Auxiliary register 1 (address A2H) bit allocation
AUXR1 - Auxiliary register 1 (address A2H) bit descriptions
Symbol
-
GF2
0
-
DPS
7
-
DPS = 0
DPS = 1
AUXR1 / bit0
Rev. 05 — 15 December 2009
DPS
6
-
DPTR0
DPTR1
Description
Reserved for future use. Should be set to ‘0’ by user programs.
General purpose user-defined flag.
This bit contains a hard-wired ‘0’. Allows toggling of the DPS bit by
incrementing AUXR1, without interfering with other bits in the register.
Reserved for future use. Should be set to ‘0’ by user programs.
Data pointer select. Chooses one of two Data Pointers for use by the
program. See text for details.
5
-
DPH
83H
P89LV51RB2/RC2/RD2
4
-
DPL
82H
8-bit microcontrollers with 80C51 core
DPTR1
DPTR0
GF2
3
external data memory
2
0
002aaa518
© NXP B.V. 2009. All rights reserved.
1
-
DPS
20 of 76
0

Related parts for P89LV51RD2FA,512