P89LV51RD2FA,512 NXP Semiconductors, P89LV51RD2FA,512 Datasheet - Page 6

• Manufacturer Part Number: P89LV51RD2FA,512
• Description: IC 80C51 MCU 1024 RAM 44PLCC
• Manufacturer: NXP Semiconductors
• Series: 89LVr

Specifications of P89LV51RD2FA,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: P89LV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Package: 44PLCC
• Device Core: 80C51
• Family Name: 89LV
• Maximum Speed: 40 MHz
• For Use With: 622-1017 - BOARD 44-ZIF PLCC SOCKET622-1008 - BOARD FOR LPC9103 10-HVSON
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 935274176512; P89LV51RD2FA; P89LV51RD2FA

NXP Semiconductors
Table 3.
P89LV51RB2_RC2_RD2_5
Product data sheet
Symbol
P0.0 to P0.7
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
P1.0 to P1.7
P1.0/T2
P1.1/T2EX
P1.2/ECI
P89LV51RB2/RC2/RD2 pin description
5.2 Pin description
Pin
TQFP44
37
36
35
34
33
32
31
30
40
41
42
PLCC44
43
42
41
40
39
38
37
36
2
3
4
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O with
internal
pull-up
I
I/O
I/O
I
I/O
I
Rev. 05 — 15 December 2009
Description
Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. Port 0
pins that have ‘1’s written to them float, and in this state can be
used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external
code and data memory. In this application, it uses strong internal
pull-ups when transitioning to ‘1’s. Port 0 also receives the code
bytes during the external host mode programming, and outputs
the code bytes during the external host mode verification.
External pull-ups are required during program verification or as a
general purpose I/O port.
P0.0 — Port 0 bit 0.
AD0 — Address/data bit 0.
P0.1 — Port 0 bit 1.
AD1 — Address/data bit 1.
P0.2 — Port 0 bit 2.
AD2 — Address/data bit 2.
P0.3 — Port 0 bit 3.
AD3 — Address/data bit 3.
P0.4 — Port 0 bit 4.
AD4 — Address/data bit 4.
P0.5 — Port 0 bit 5.
AD5 — Address/data bit 5.
P0.6 — Port 0 bit 6.
AD6 — Address/data bit 6.
P0.7 — Port 0 bit 7.
AD7 — Address/data bit 7.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pull-ups. The Port 1 pins are pulled high by the internal pull-ups
when ‘1’s are written to them and can be used as inputs in this
state. As inputs, Port 1 pins that are externally pulled LOW will
source current (I
P1.7 have a high current drive of 16 mA. Port 1 also receives the
low-order address bytes during the external host mode
programming and verification.
P1.0 — Port 1 bit 0.
T2 — External count input to Timer/counter 2 or Clock-out from
Timer/counter 2.
P1.1 — Port 1 bit 1.
T2EX: Timer/counter 2 capture/reload trigger and direction
control input.
P1.2 — Port 1 bit 2.
ECI — External clock input. This signal is the external clock input
for the PCA.
P89LV51RB2/RC2/RD2
IL
) because of the internal pull-ups. P1.5, P1.6,
8-bit microcontrollers with 80C51 core
© NXP B.V. 2009. All rights reserved.
6 of 76