LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 493
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- Current page: 493 of 792
- Download datasheet (5Mb)
NXP Semiconductors
UM10237_4
User manual
8.14 Transmit Identifier Register (CAN1TID[1/2/3] - 0xE004 40[34/44/54],
8.15 Transmit Data Register A (CAN1TDA[1/2/3] - 0xE004 40[38/48/58],
CAN2TID[1/2/3] - 0xE004 80[34/44/54])
When the corresponding TBS bit in CANxSR is 1, software can write to one of these
registers to define the Identifier field of the next transmit message. Bits not listed read as 0
and should be written as 0. The register assumes two different formats depending on the
FF bit in CANTFI.
In Standard Frame Format messages, the CAN Identifier consists of 11 bits (ID.28 to
ID.18), and in Extended Frame Format messages, the CAN identifier consists of 29 bits
(ID.28 to ID.0). ID.28 is the most significant bit, and it is transmitted first on the bus during
the arbitration process. The Identifier acts as the message's name, used in a receiver for
acceptance filtering, and also determines the bus access priority during the arbitration
process.
Table 434. Transfer Identifier Register (CAN1TID[1/2/3] - address 0xE004 40[34/44/54],
Table 435. Transfer Identifier register when FF = 1
CAN2TDA[1/2/3] - 0xE004 80[38/48/58])
When the corresponding TBS bit in CANSR is 1, software can write to one of these
registers to define the first 1 - 4 data bytes of the next transmit message. The Data Length
Code defines the number of transferred data bytes. The first bit transmitted is the most
significant bit of TX Data Byte 1.
Table 436. Transmit Data Register A (CAN1TDA[1/2/3] - address 0xE004 40[38/48/58],
Bit
10:0
31:11
Bit
28:0
31:29 -
Bit
7:0
15;8
23:16 Data 3
31:24 Data 4
Symbol Function
Data 1
Data 2
Symbol Function
ID
-
Symbol Function
ID
CAN2TID[1/2/3] - address 0xE004 80[34/44/54]) bit description
CAN2TDA[1/2/3] - address 0xE004 80[38/48/58]) bit description
If RTR = 0 and DLC
byte is sent as the first Data byte of the next transmit message.
If RTR = 0 and DLC
byte is sent as the 2nd Data byte of the next transmit message.
If RTR = 0 and DLC
byte is sent as the 3rd Data byte of the next transmit message.
If RTR = 0 and DLC
byte is sent as the 4th Data byte of the next transmit message.
The 11 bit Identifier to be sent in the next transmit message.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The 29 bit Identifier to be sent in the next transmit message.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
≥
≥
≥
≥
0001 in the corresponding CANxTFI, this
0010 in the corresponding CANxTFI, this
0011 in the corresponding CANxTFI, this
0100 in the corresponding CANxTFI, this
Chapter 18: LPC24XX CAN controllers CAN1/2
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
Value
0
0
0
0
Reset
Value
0
NA
Reset
Value
0
NA
493 of 792
RM
Set
X
X
X
X
RM
Set
X
RM
Set
X
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