LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 571
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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UM10237_4
User manual
6.14 FIFO Counter Register (MCIFifoCnt - 0xE008 C048)
6.15 Data FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008 C0BC)
Table 506: Interrupt Mask registers (MCIMask0 - address 0xE008 C03C) bit description
The MCIFifoCnt register contains the remaining number of words to be written to or read
from the FIFO. The FIFO counter loads the value from the data length register (see
Section 21–6.8 “Data Length Register (MCIDataLength - 0xE008
Enable bit is set in the data control register. If the data length is not word aligned (multiple
of 4), the remaining 1 to 3 bytes are regarded as a word.
assignment of the MCIFifoCnt register.
Table 507: FIFO Counter register (MCIFifoCnt - address 0xE008 C048) bit description
The receive and transmit FIFOs can be read or written as 32 bit wide registers. The FIFOs
contain 16 entries on 16 sequential addresses. This allows the microprocessor to use its
load and store multiple operands to read/write to the FIFO.
assignment of the MCIFIFO register.
Table 508: Data FIFO register (MCIFIFO - address 0xE008 C080 to 0xE008 C0BC) bit
Bit
8
9
10
11
12
13
14
15
16
17
18
19
20
21
31:22
Bit
14:0
31:15
Bit
31:0
Symbol
Mask8
Mask9
Mask10
Mask11
Mask12
Mask13
Mask14
Mask15
Mask16
Mask17
Mask18
Mask19
Mask20
Mask21
-
Symbol
DataCount
-
Symbol
Data
description
Description
FIFO data.
Description
Remaining data
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Description
Mask DataEnd flag.
Mask StartBitErr flag.
Mask DataBlockEnd flag.
Mask CmdActive flag.
Mask TxActive flag.
Mask RxActive flag.
Mask TxFifoHalfEmpty flag.
Mask RxFifoHalfFull flag.
Mask TxFifoFull flag.
Mask RxFifoFull flag.
Mask TxFifoEmpty flag.
Mask RxFifoEmpty flag.
Mask TxDataAvlbl flag.
Mask RxDataAvlbl flag.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 21: LPC24XX SD/MMC card interface
Table 21–507
Table 21–508
C028)”) when the
UM10237
© NXP B.V. 2009. All rights reserved.
shows the bit
shows the bit
Reset Value
0x0000 0000
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NA
Reset
Value
0x0000
NA
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