LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 615
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
5.3 Transmit FIFO Register (I2STXFIFO - 0xE008 8008)
5.4 Receive FIFO Register (I2SRXFIFO - 0xE008 800C)
5.5 Status Feedback Register (I2SSTATE - 0xE008 8010)
Table 533: Digital Audio Input register (I2SDAI - address 0xE008 8004) bit description
The I2STXFIFO register provides access to the transmit FIFO. The function of bits in
I2STXFIFO are shown in
Table 534: Transmit FIFO register (I2STXFIFO - address 0xE008 8008) bit description
The I2SRXFIFO register provides access to the receive FIFO. The function of bits in
I2SRXFIFO are shown in
Table 535: Receive FIFO register (I2RXFIFO - address 0xE008 800C) bit description
The I2SSTATE register provides status information about the I2S interface. The meaning
of bits in I2SSTATE are shown in
Table 536: Status Feedback register (I2SSTATE - address 0xE008 8010) bit description
Bit
1:0
2
3
4
5
14:6
15
Bit
31:0
Bit
31:0 I2SRXFIFO
Bit
0
1
2
7:3
Symbol
Symbol
I2STXFIFO
Symbol
irq
dmareq1
dmareq2
Unused
Symbol
wordwidth
mono
stop
reset
ws_sel
ws_halfperiod
Unused
Description
This bit reflects the presence of Receive Interrupt or Transmit Interrupt. 0
This bit reflects the presence of Receive or Transmit DMA Request 1.
This bit reflects the presence of Receive or Transmit DMA Request 2.
Unused.
Description
8
Description
8
Value Description
×
Rev. 04 — 26 August 2009
×
00
01
10
11
32 bits transmit FIFO.
32 bits transmit FIFO.
Table
Table
Selects the number of bytes in data as follows:
8 bit data
16 bit data
Reserved, do not use this setting
32 bit data
When one, data is of monaural format. When zero, the
data is in stereo format.
Disables accesses on FIFOs, places the transmit
channel in mute mode.
Asynchronously reset the transmit channel and FIFO.
When 0 master mode, when 1 slave mode.
Word select half period minus one, i.e. WS 64clk period
-> ws_halfperiod = 31.
Unused.
23–534.
23–535.
Table
23–536.
Chapter 23: LPC24XX I
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
level = 0
Reset Value
Level = 0
2
S interface
Reset
Value
01
0
0
0
1
0x1F
1
615 of 792
0
0
0
Reset
Value
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