PXAG37KFA,512 NXP Semiconductors, PXAG37KFA,512 Datasheet - Page 18

• Manufacturer Part Number: PXAG37KFA,512
• Description: IC XA MCU 16BIT 32K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: XAr

Specifications of PXAG37KFA,512

• Core Processor: XA
• Core Size: 16-Bit
• Speed: 30MHz
• Connectivity: UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: PXAG3x
• Core: 80C51
• Data Bus Width: 16 bit
• Data Ram Size: 512 B
• Interface Type: UART
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: XA
• Device Core: 80C51
• Device Core Size: 16b
• Frequency (max): 30MHz
• Total Internal Ram Size: 512Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1096-5; 935263502512; PXAG37KFA

1. The maximum baud rate for a UART in mode 1 or 3 is Osc/64.
2. The lowest possible baud rate (for a given oscillator frequency
3. The timer reload value may never be larger than the timer range.
4. If a timer reload value calculation gives a negative or fractional
Philips Semiconductors
CLOCKING SCHEME/BAUD RATE GENERATION
The XA UARTS clock rates are determined by either a fixed division
(modes 0 and 2) of the oscillator clock or by the Timer 1 or Timer 2
overflow rate (modes 1 and 3).
The clock for the UARTs in XA runs at 16x the Baud rate. If the
timers are used as the source for Baud Clock, since maximum
speed of timers/Baud Clock is Osc/4, the maximum baud rate is
timer overflow divided by 16 i.e. Osc/64.
In Mode 0, it is fixed at Osc/16. In Mode 2, however, the fixed rate is
Osc/32.
Baud Rate for UART Mode 0:
Baud Rate calculation for UART Mode 1 and 3:
The timer reload value may be calculated as follows:
NOTES:
Baud Rate for UART Mode 2:
2002 Mar 25
Pre-scaler
for all Timers T0 1 2
for all Timers T0,1,2
controlled by PT1, PT0
controlled by PT1, PT0
bits in SCR
XA 16-bit microcontroller family
32K OTP, 512 B RAM, watchdog, 2 UARTs
SnSTAT Address: S0STAT 421
Bit Addressable
Reset Value: 00H
and N value) may be found by using a timer reload value of 0.
result, the baud rate requested is not possible at the given
oscillator frequency and N value.
Baud_Rate = Osc/16
Baud_Rate = Timer_Rate/16
Timer_Rate = Osc/(N*(Timer_Range– Timer_Reload_Value))
where N = the TCLK prescaler value: 4, 16, or 64.
and Timer_Range = 256 for timer 1 in mode 2.
Timer_Reload_Value = Timer_Range–(Osc/(Baud_Rate*N*16))
Baud_Rate = Osc/32
SnSTAT.0 STINTn
BIT
SnSTAT.3 FEn
SnSTAT.2 BRn
SnSTAT.1 OEn
SYMBOL FUNCTION
S1STAT 425
65536 for timer 1 in mode 0 and timer 2
in count up mode.
00
01
10
11
Framing Error flag is set when the receiver fails to see a valid STOP bit at the end of the frame.
Cleared by software.
Break Detect flag is set if a character is received with all bits (including STOP bit) being logic ‘0’. Thus
it gives a “Start of Break Detect” on bit 8 for Mode 1 and bit 9 for Modes 2 and 3. The break detect
feature operates independently of the UARTs and provides the START of Break Detect status bit that
a user program may poll. Cleared by software.
Overrun Error flag is set if a new character is received in the receiver buffer while it is still full (before
the software has read the previous character from the buffer), i.e., when bit 8 of a new byte is
received while RI in SnCON is still set. Cleared by software.
This flag must be set to enable any of the above status flags to generate a receive interrupt (RIn). The
only way it can be cleared is by a software write to this register.
Figure 11. Serial Port Extended Status (SnSTAT) Register
MSB
Osc/4
Osc/16
Osc/64
reserved
—
(See also Figure 13 regarding Framing Error flag)
—
—
16
—
Using Timer 2 to Generate Baud Rates
Timer T2 is a 16-bit up/down counter in XA. As a baud rate
generator, timer 2 is selected as a clock source for either/both
UART0 and UART1 transmitters and/or receivers by setting TCLKn
and/or RCLKn in T2CON and T2MOD. As the baud rate generator,
T2 is incremented as Osc/N where N = 4, 16 or 64 depending on
TCLK as programmed in the SCR bits PT1, and PTO. So, if T2 is
the source of one UART, the other UART could be clocked by either
T1 overflow or fixed clock, and the UARTs could run independently
with different baud rates.
Prescaler Select for Timer Clock (TCLK)
T2MOD
T2CON
0x418
0x419
0x440
SCR
FEn
BRn
OEn
RCLK0
RCLK1
PT1
bit5
bit5
bit3
STINTn
LSB
TCLK0
TCLK1
PT0
bit4
bit4
bit2
XA-G37
SU00607B
Product data