EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 545
EP9307-IRZ
Manufacturer Part Number
EP9307-IRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-IRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
3
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1256
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9307-IRZ
Manufacturer:
CIRRUS
Quantity:
3 468
Company:
Part Number:
EP9307-IRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
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- EP9307-CRZ PDF datasheet #3
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DS785UM1
Address:
Default:
Definition:
Bit Descriptions:
0x808C_0018 - Read Only
0x0000_0000
UART Flag Register
RSVD:
TXFE:
RXFF:
TXFF:
RXFE:
BUSY:
DCD:
DSR:
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
Transmit FIFO Empty. The meaning of this bit depends on
the state of the FEN bit in the UART1LinCtrlHigh register.
If the FIFO is disabled, this bit is set when the transmit
holding register is empty. If the FIFO is enabled, the TXFE
bit is set when the transmit FIFO is empty.
Receive FIFO Full. The meaning of this bit depends on the
state of the FEN bit in the UART1LinCtrlHigh register. If
the FIFO is disabled, this bit is set when the receive
holding register is full. If the FIFO is enabled, the RXFF bit
is set when the receive FIFO is full.
Transmit FIFO Full. The meaning of this bit depends on
the state of the FEN bit in the UART1LinCtrlHigh register.
If the FIFO is disabled, this bit is set when the transmit
holding register is full. If the FIFO is enabled, the TXFF bit
is set when the transmit FIFO is full.
Receive FIFO Empty. The meaning of this bit depends on
the state of the FEN bit in the UART1LinCtrlHigh register.
If the FIFO is disabled, this bit is set when the receive
holding register is empty. If the FIFO is enabled, the RXFE
bit is set when the receive FIFO is empty.
UART Busy. If this bit is set to 1, the UART is busy
transmitting data. This bit remains set until the complete
byte, including all the stop bits, has been sent from the
shift register. This bit is set as soon as the transmit FIFO
becomes non-empty (regardless of whether the UART is
enabled or not).
Data Carrier Detect status. This bit is the complement of
the UART data carrier detect (nUARTDCD) modem status
input. That is, the bit is 1 when the modem status input is
0.
Data Set Ready status. This bit is the complement of the
UART data set ready (nUARTDSR) modem status input.
That is, the bit is 1 when the modem status input is 0.
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
14-23
14
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