EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 646
EP9307-IRZ
Manufacturer Part Number
EP9307-IRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-IRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
3
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1256
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9307-IRZ
Manufacturer:
CIRRUS
Quantity:
3 468
Company:
Part Number:
EP9307-IRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
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- Download datasheet (13Mb)
19
19-4
Watchdog Timer
EP93xx User’s Guide
READ ONLY BIT FIELDS
PLSDSN:
OVRID:
SWDIS:
HWDIS:
URST:
3KRST:
WD:
Copyright 2007 Cirrus Logic
Pulse Disable Not. The Watchdog internal PLSDIS bit
monitors the HW_PULSE_DISABLEn latch status in the
watchdog module. This provides status of the hardware
pulse duration disable function. Active low means that the
reset pulse is disabled.
Software Override of the hardware watchdog disable. The
OVRID bit monitors the SW_OVERIDE_HW_DISABLE
register status in the watchdog module. This provides
status of the watchdog software disable overriding the
hardware disable function. This bit is active high when the
software disable is overriding the hardware disable.
Software Watchdog Disable. The SWDIS bit monitors the
SW_WATCHDOG_DISABLE register status in the
watchdog module. This provides status of the watchdog
software disable function. This bit is active high when the
watchdog is software disabled.
Hardware Watchdog Disable. The HWDIS bit monitors the
HW_WATCHDOG_DISABLEN latch status in the
watchdog module. This provides status of the watchdog
hardware disable function. This bit is active high when the
watchdog is hardware disabled.
User Reset Status flip flop. Read only. When “1”, this bit
indicates that the last reset was generated by the user
reset signal (externally on RSTOn). This bit is not cleared
by any resets other than power on reset, PWR_RESETn.
Three-Key Reset Status flip flop. Read only. When “1”, this
bit indicates that the last reset signal was generated by a
three-key reset from the key scan controller. This bit is not
cleared by any resets other than power on reset,
PWR_RESETn.
Watchdog Reset Status flip flop. Read only. When “1”, this
bit indicates that the last reset was generated because of
a watch dog time out. This bit is not cleared by any resets
other than power on reset, PWR_RESETn.
DS785UM1
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