EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 805
EP9307-IRZ
Manufacturer Part Number
EP9307-IRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-IRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
3
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1256
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9307-IRZ
Manufacturer:
CIRRUS
Quantity:
3 468
Company:
Part Number:
EP9307-IRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
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- Download datasheet (13Mb)
RawIntStsX
IntStsX
DS785UM1
31
15
31
15
Bit Descriptions:
Address:
Definition:
Bit Descriptions:
Address:
Each bit in the register reports whether an interrupt would be signalled if the interrupt were
enabled for the corresponding port; a set bit indicates that an interrupt would be signalled.
The value reported is unaffected by whether interrupts are enabled or disabled. How a bit is
set depends on the interrupt type. If the interrupt is level sensitive active high, it reflects the
pin value. If level sensitive active low, it reflects the inverse of the pin value. If the interrupt is
edge triggered, the bit latches a one whenever the proper level change occurs. How a bit is
cleared also depends on the interrupt type. When an interrupt is level sensitive, it is cleared
when not asserted. When edge triggered, it is cleared by writing the corresponding bit in
GPIOxEOI. Note that the value of a bit is a debounced value if debouncing is enabled.
30
14
30
14
29
13
29
13
28
12
28
12
RSVD
RSVD
RSVD:
PxINTDB:
RawIntStsA: 0x8084_00A4 - Read Only
RawIntStsB: 0x8084_00C0 - Read Only
RawIntStsF: 0x8084_0060 - Read Only
RSVD:
PxINTRS:
27
11
27
11
26
10
26
10
25
25
9
9
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
Interrupt debounce enable.
Reserved. Unknown During Read.
Raw Interrupt Status.
24
24
8
8
RSVD
RSVD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
PxINTRS
PxINTS
19
19
3
3
EP93xx User’s Guide
18
18
2
2
GPIO Interface
17
17
1
1
28-15
16
16
0
0
28
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