EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 12
EP9312-IB
Manufacturer Part Number
EP9312-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-IB
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1259
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 12 of 824
- Download datasheet (13Mb)
EP93xx User’s Guide
Chapter 20. Real Time Clock With Software Trim ............................................ 20-1
Chapter 21. I
Chapter 22. AC’97 Controller.............................................................................. 22-1
Chapter 23. Synchronous Serial Port ................................................................ 23-1
xii
20.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-4
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1
21.2 I
21.3 I
21.4 I
21.5 I
21.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-10
21.7 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-12
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1
22.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-3
22.3 System Loopback Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-5
22.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-5
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-1
23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-1
23.3 SSP Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-2
23.4 SSP Pin Multiplex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-2
2
2
2
2
20.1.1 Software Trim ..............................................................................................................20-1
20.1.2 Reset Control...............................................................................................................20-4
21.3.1 Receiver FIFO’s...........................................................................................................21-6
21.5.1 Example of the Bit Clock Generation...........................................................................21-9
21.5.2 Example of Right Justified LRCK format ...................................................................21-10
21.7.1 I
21.7.2 I
21.7.3 I
21.7.4 I
22.2.1 Channel Interrupts .......................................................................................................22-3
22.2.2 Global Interrupts ..........................................................................................................22-4
S Transmitter Channel Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-2
S Receiver Channel Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-5
S Master Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-7
S Bit Clock Rate Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-9
2
S Controller................................................................................... 21-1
2
2
2
2
S TX Registers........................................................................................................21-12
S RX Registers .......................................................................................................21-19
S Configuration and Status Registers.....................................................................21-25
S Global Status Registers.......................................................................................21-29
20.1.1.1 Software Compensation ............................................................................20-2
20.1.1.2 Oscillator Frequency Calibration................................................................20-2
20.1.1.3 RTCSWComp Value Determination ..........................................................20-2
20.1.1.4 Example - Measured Value Split Into Integer and Fractional Component .20-3
20.1.1.5 Maximum Error Calculation vs. Real Time Clock Accuracy.......................20-3
20.1.1.6 Real-Time Interrupt....................................................................................20-3
22.2.1.1 RIS.............................................................................................................22-3
22.2.1.2 TIS .............................................................................................................22-3
22.2.1.3 RTIS...........................................................................................................22-4
22.2.1.4 TCIS...........................................................................................................22-4
22.2.2.1 CODECREADY .........................................................................................22-4
22.2.2.2 WINT..........................................................................................................22-4
22.2.2.3 GPIOINT ....................................................................................................22-4
22.2.2.4 GPIOTXCOMPLETE .................................................................................22-5
22.2.2.5 SLOT2INT..................................................................................................22-5
22.2.2.6 SLOT1TXCOMPLETE ...............................................................................22-5
22.2.2.7 SLOT2TXCOMPLETE ...............................................................................22-5
©
Copyright 2007 Cirrus Logic, Inc.
DS785UM1
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