EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 489
EP9312-IB
Manufacturer Part Number
EP9312-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-IB
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1259
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
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- Download datasheet (13Mb)
DS785UM1
Bit Descriptions:
RSVD:
IDCY:
WST1:
RBLE:
WST2:
Copyright 2007 Cirrus Logic
• A single Read or Write access, or
• The first Read or Write access of a burst-of-four
Reserved - Unknown During Read
Idle Cycle - Read/Write
The value written to this field specifies the memory data
bus turnaround time between a Read access and a Write
access. The turnaround time is specified by (IDCY + 1)
HCLKs. For example, if IDCY = 0xA, the turnaround time
is 10 + 1 = 11 cycles of HCLK.
Wait States1 - Read/Write
The value written to this field specifies the ‘number of
HCLK cycles, minus 1’ that are inserted as wait cycles into
the timing for:
The number of wait cycles is specified by (WST1 + 1)
HCLKs. For example, if WST1 = 0x3, 3 + 1 = 4 cycles of
HCLK are inserted into the access timing.
On reset, this field defaults to 0x1F (slowest access) to
enable booting from ROM or FLASH memory device
types.
Read Byte Lane Enable - Read/Write
The value written to this bit specifies the output values on
the DQMn[3:0] pins during a Read access:
0 - DQMn[3:0] pins are all driven HIGH during memory
Reads (default at reset for bank 1-3,6,7)
1 - DQMn[3:0] pins are all driven LOW during memory
Reads (default at reset for bank 0)
For memory Writes, this bit must written to ‘1’.
Wait States2 - Read/Write
The value in this field specifies the ‘number of HCLK
cycles, minus 1’ that are inserted as wait cycles into the
timing for each of the 2nd, 3rd, and 4th accesses of Read
or Write burst-of-four accesses.
accesses.
Static Memory Controller
EP93xx User’s Guide
12-11
12
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