EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 591
EP9312-IB
Manufacturer Part Number
EP9312-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-IB
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1259
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 591 of 824
- Download datasheet (13Mb)
DS785UM1
CRCApd:
IDLE:
AME:
RXE:
TXE:
TUS:
CRCE:
CRCS:
Copyright 2007 Cirrus Logic
CRC pass through.
0 - Do not pass received CRC to CPU.
1 - Pass received CRC to CPU.
Idle mode.
0 - Idle-in Mark mode - When HDLC is idle (not
transmitting start or stop flags or packets), hold the
transmit data pin high.
1 - Idle-in Flag mode - When HDLC is idle, transmit
continuous flags.
Address Match Enable. Activates address matching on
received frames.
00 - No address matching
01 - 4 x 1 byte matching
10 - 2 x 2 byte matching
11 - Undefined, no matching
HDLC Receive Enable.
0 - Disable HDLC RX. If UART is still enabled, UART may
still receive normally.
1 - Enable HDLC RX.
HDLC Transmit Enable.
0 - Disable HDLC TX. If UART is still enabled, UART may
still transmit normally.
1 - Enable HDLC TX.
Transmit FIFO Underrun Select
0 - TX FIFO underrun causes CRC (if enabled) and stop
flag to be transmitted.
1 - TX FIFO underrun causes abort (escape-flag) to be
transmitted.
CRC enable.
0 - No CRC generated by HDLC TX or expected by HDLC
RX.
1 - HDLC TX automatically generates and sends a CRC at
the end of a packet, and HDLC RX expects a CRC at the
end of a packet.
CRC size.
0 - CRC-16: x
1 - CRC-32: x
x
8
+ x
7
+ x
5
+ x
16
32
4
+ x
+ x
+ x
12
26
2
+ x + 1
+ x
+ x
5
23
+ 1
+ x
22
+ x
UART3 With HDLC Encoder
16
+ x
EP93xx User’s Guide
12
+ x
11
+ x
10
16-15
+
16
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