EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 602
EP9312-IB
Manufacturer Part Number
EP9312-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-IB
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1259
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
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- Download datasheet (13Mb)
17
17-6
17.3.2.3.2 End of Frame Interrupt
17.3.2.3.3 End of Frame: Using Programmed I/O
17.3.2.3.4 Error Conditions
IrDA
EP93xx User’s Guide
The Receive Frame Complete (RFC) interrupt is generated when the last data in a frame is
read from the receive FIFO. To check whether the frame was received correctly (no errors)
and for information on frame size, the Receive Information Buffer register (IrRIB) must be
read by the interrupt service routine. This also clears the RFC interrupt condition.
If interrupt driven programmed I/O is used instead of DMA, every time the Receive Buffer
Service (RFS) interrupt is serviced the IrFlag register must be read before the IrData register,
if the IrFlag values are needed. Their Flag register gives information about error conditions
that correspond to the data value at the head of the receive FIFO.
Receive error conditions do not generate interrupts. Reading the IrData word clears the
IrFlag register bits listed below.
Note: By the time the ARM Core responds to this interrupt, the interface may have already
Note: The IrRIB registers stores status flags for a complete frame.
started reception of a new frame.
Set up DMA
Enable Ir Receive Set the Receive Enable bit (RXE) in IrEnable.
Receiver Abort Detected When set, this indicates that the transmitter sent an
Receiver Overrun This indicates that data has not been read for the IrData
CRC Error
Frame Error (FIR only) This indicates that a framing error has been detected.
Copyright 2007 Cirrus Logic
Set up a DMA buffer (the buffer should be greater than
twice the maximum possible size of received frames).
Enable DMA.
Alternatively, two buffers may be used which are each the
maximum possible frame size long. The DMA would then
be programmed to switch between the two buffers.
abort signal during frame transmission.
register in time and has resulted in data loss from the
frame. When this occurs the interface automatically
discards the remainder of the incoming frame.
If the CRC for the received data does not match the CRC
value contained in the incoming data stream this condition
will occur.
DS785UM1
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