EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 710
EP9312-IB
Manufacturer Part Number
EP9312-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-IB
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1259
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 710 of 824
- Download datasheet (13Mb)
22
AC97Reset
22-22
AC’97 Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x8088_00A0 - Read/Write
Controller Reset Register. The AC’97 Controller RESET register is a
read/write register that controls various functions within the AC’97 Controller
of the RESET port. All the register bits are cleared to “0” when reset.
RSVD:
EFORCER:
FORCEDRESET: If the EFORCER bit is set to “1”, the RESET port will follow
TIMEDRESET:
27
11
26
10
Copyright 2007 Cirrus Logic
RSVD
25
9
Reserved. Unknown During Read.
Enable for the Forced RESET bit.
1 - FORCEDRESET become active
0 - FORCEDRESET has no effect.
whatever value is written to this bit. If this mechanism is
used to control the RESET port, it is up to software to
ensure that the signal is high long enough to meet the
specification of the external device.
This bit has priority over the TIMEDRESET bit.
If this bit is set to “1”, the RESET port is forced to “0” for
five pulses of the 2.9491 MHz clock
(0.339 µs x 5 = 1.695 µs maximum reset pulse and
1.356 µs minimum reset pulse using this 2.9491 MHz
clock). After which this bit is zeroed.
24
8
23
7
22
6
21
5
20
4
19
3
EFORCER
18
2
FORCED
RESET
17
1
DS785UM1
RESET
TIMED
16
0
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