EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 717
EP9312-IB
Manufacturer Part Number
EP9312-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-IB
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1259
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
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- Download datasheet (13Mb)
DS785UM1
23.5.6 Motorola
23.5.6.1 SPO Clock Polarity
23.5.6.2 SPH Clock Phase
23.5.7 Motorola SPI Format with SPO=0, SPH=0
SFRMOUT /
SCLKOUT /
The Motorola SPI interface is a four-wire interface where the SFRMOUT signal behaves as a
slave select. The main feature of the Motorola SPI format is that the inactive state and phase
of the SCLKOUT signal are programmable through the SPO and SPH bits within the control
register,
When the SPO clock polarity control bit is LOW, it produces a steady state low value on the
SCLKOUT pin. If the SPO clock polarity control bit is HIGH, a steady state high value is
placed on the SCLKOUT pin when data is not being transferred.
The SPH control bit selects the clock edge that captures data and allows it to change state. It
has the most impact on the first bit transmitted by either allowing or not allowing a clock
transition before the first data capture edge.
When the SPH phase control bit is LOW, data is captured on the first clock edge transition. If
the SPH clock phase control bit is HIGH, data is captured on the second clock edge
transition.
Single and continuous transmission signal sequences for Motorola SPI format with SPO=0,
SPH=0 are shown in
SFRMIN
SCLKIN
SSPTXD
SSPRXD
SSPOE
Figure 23-3. Motorola SPI Frame Format (Single Transfer) with SPO=0 and SPH=0
“SSPCR0” on page
®
SPI Frame Format
MS B
MS B
Figure 23-3
23-13.
Copyright 2007 Cirrus Logic
and
Figure 23-4 on page
4 t o 16 bi t s
23-6.
Synchronous Serial Port
EP93xx User’s Guide
LS B
LS B
Q
23-5
23
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