W78E052DDG Nuvoton Technology Corporation of America, W78E052DDG Datasheet - Page 31

• Manufacturer Part Number: W78E052DDG
• Description: IC MCU 8-BIT 8K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E052DDG

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Timer 2 Control
Mnemonic: T2CON
Program Verify APROM
Read APROM
Bit:
BIT
7
6
5
4
3
2
1
0
7
TF2
NAME
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C T
CP RL
/ 2
/
2
6
EXF2
Timer 2 Run Control. This bit enables/disables the operation of timer 2. Clear-
FUNCTION
Timer 2 overflow flag: This bit is set when Timer 2 overflows. It is also set
when the count is equal to the capture register in down count mode. It can be
set only if RCLK and TCLK are both 0. It is cleared only by software. Software
can also set or clear this bit.
Timer 2 External Flag: A negative transition on the T2EX pin (P1.1) or timer 2
overflow will cause this flag to set based on the CP RL
bits. If set by a negative transition, this flag must be cleared by software. Set-
ting this bit in software or detection of a negative transition on T2EX pin will
force a timer interrupt if enabled.
Receive Clock Flag: This bit determines the serial port 0 time-base when re-
ceiving data in serial modes 1 or 3. If it is 0, then timer 1 overflow is used for
baud rate generation, otherwise timer 2 overflow is used. Setting this bit forces
timer 2 in baud rate generator mode.
Transmit Clock Flag: This bit determines the serial port 0 time-base when
transmitting data in modes 1 and 3. If it is set to 0, the timer 1 overflow is used
to generate the baud rate clock otherwise timer 2 overflow is used. Setting this
bit forces timer 2 in baud rate generator mode.
Timer 2 External Enable. This bit enables the capture/reload function on the
T2EX pin if Timer 2 is not generating baud clocks for the serial port. If this bit
is 0, then the T2EX pin will be ignored, otherwise a negative transition de-
tected on the T2EX pin will result in capture or reload.
ing this bit will halt the timer 2 and preserve the current count in TH2, TL2.
Counter/Timer Select. This bit determines whether timer 2 will function as a
timer or a counter. Independent of this bit, the timer will run at 2 clocks per tick
when used in baud rate generator mode.
Capture/Reload Select. This bit determines whether the capture or reload
function will be used for timer 2. If either RCLK or TCLK is set, this bit will be
ignored and the timer will function in an auto-reload mode following each over-
flow. If the bit is 0 then auto-reload will occur when timer 2 overflows or a fal-
ling edge is detected on T2EX pin if EXEN2 = 1. If this bit is 1, then timer 2
captures will occur when a falling edge is detected on T2EX pin if EXEN2 =
1.
0
0
5
RCLK
W78E054D/W78E052D/W78E051D Data Sheet
4
TCLK
0
0
- 31 -
3
EXEN2
1010
0000
Publication Release Date: Dec 29, 2009
2
TR2
Address in
Address in
/
2 , EXEN2 and DCEN
1
C T
/ 2
Address: C8h
Revision A09
Data out
Data out
0
CP RL
/
2