W78E052DDG Nuvoton Technology Corporation of America, W78E052DDG Datasheet - Page 33

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W78E052DDG

Manufacturer Part Number
W78E052DDG
Description
IC MCU 8-BIT 8K FLASH 40-DIP
Manufacturer
Nuvoton Technology Corporation of America
Series
W78r
Datasheet

Specifications of W78E052DDG

Core Processor
8052
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR, WDT
Number Of I /o
36
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

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0
Program Status Word
Mnemonic: PSW
Port 4
Mnemonic: P4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port ad-
dress is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are alter-
native function pins. It can be used as general I/O pins or external interrupt input sources ( INT2 ,
ACCUMULATOR
Mnemonic: ACC
INT3 ).
Bit
BIT
7-0
Bit:
BIT
Bit:
Bit:
7
6
5
4
3
2
1
0
Name
NAME
CY
AC
F0
RS1
RS0
OV
F1
P
NAME
TH2.[7:0]
7
CY
7
-
7
ACC.7
FUNCTION
Carry flag:
Set for an arithmetic operation which results in a carry being generated from the
ALU. It is also used as the accumulator for the bit operations.
Auxiliary carry:
Set when the previous operation resulted in a carry from the high order nibble.
User flag 0:
The General purpose flag that can be set or cleared by the user.
Register bank select bits:
Register bank select bits:
Overflow flag:
Set when a carry was generated from the seventh bit but not from the 8
result of the previous operation, or vice-versa.
User Flag 1:
The General purpose flag that can be set or cleared by the user by software.
Parity flag:
Set/cleared by hardware to indicate odd/even number of 1’s in the accumulator.
Function
6
AC
6
-
6
ACC.6
FUNCTION
Timer 2 MSB
5
F0
5
-
5
ACC.5
W78E054D/W78E052D/W78E051D Data Sheet
4
RS1
4
-
4
ACC.4
- 33 -
3
RS0
3
P4.3
3
ACC.3
Publication Release Date: Dec 29, 2009
2
OV
2
P4.2
2
ACC.2
1
F1
1
P4.1
1
ACC.1
Address: D8h
Address: D0h
th
Address: E0h
bit as a
Revision A09
0
P
0
P4.0
0
ACC.0

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