ST7FLITEUS5B6 STMicroelectronics, ST7FLITEUS5B6 Datasheet - Page 50
ST7FLITEUS5B6
Manufacturer Part Number
ST7FLITEUS5B6
Description
MCU 8BIT 1KB FLASH 128KB 8-DIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.STEVAL-IFS006V1.pdf
(136 pages)
Specifications of ST7FLITEUS5B6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Controller Family/series
ST7
No. Of I/o's
5
Ram Memory Size
128Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
497-6403 - BOARD EVAL 8BIT MICRO + TDE1708497-6407 - BOARD EVAL FOR VACUUM CLEANER497-5861 - EVAL BRD POWER MOSFET/8PIN MCU497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5515 - EVAL BOARD PHASE CTRL DIMMER497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Other names
497-5636-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FLITEUS5B6
Manufacturer:
STMicroelectronics
Quantity:
8
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Power saving modes
8.4
50/136
Figure 20. Wait mode flowchart
1. 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
Active-halt and Halt modes
Active-halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active-
halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following
table:
Table 14.
LTCSR TBIE
during the interrupt routine and cleared when the CC register is popped.
bit
0
0
0
1
x
Enabling/disabling Active-halt and Halt modes
ATCSR OVFIE
WFI INSTRUCTION
N
bit
0
1
1
x
x
INTERRUPT
Y
ATCSRCK1 bit ATCSRCK0 bit
OR SERVICE INTERRUPT
FETCH RESET VECTOR
64 CPU CLOCK CYCLE
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BIT
N
1
0
x
x
x
DELAY
RESET
Y
OFF
OFF
X
ON
ON
ON
ON
ON
ON
ON
0
0
1)
0
x
1
x
1
Active-halt mode disabled
Active-halt mode enabled
ST7LITEUS2, ST7LITEUS5
Meaning
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