Z8F0822PJ020SG Zilog, Z8F0822PJ020SG Datasheet - Page 125
Z8F0822PJ020SG
Manufacturer Part Number
Z8F0822PJ020SG
Description
IC ENCORE MCU FLASH 8K 28DIP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F0822PJ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Controller Family/series
Z8
No. Of I/o's
19
Ram Memory Size
1KB
Cpu Speed
20MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
Z8F082xx
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
19
Number Of Timers
2
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4208
Z8F0822PJ020SG
Z8F0822PJ020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F0822PJ020SG
Manufacturer:
Zilog
Quantity:
45
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Infrared Endec Control Register Definitions
PS022517-0508
Caution:
of minus four baud rate clocks to plus eight baud rate clocks around the expected time of
an incoming pulse. If an incoming pulse is detected inside this window this process is
repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state
and waits for the next falling edge. As each falling edge is detected, the Endec clock
counter is reset, resynchronizing the Endec to the incoming signal. This procedure allows
the Endec to tolerate jitter and baud rate errors in the incoming data stream. Resynchroniz-
ing the Endec does not alter the operation of the UART, which ultimately receives the
data. The UART is only synchronized to the incoming data stream when a Start bit is
received.
All Infrared Endec configuration and status information is set by the UART control
registers as defined in
UART Control 1 register to 1 to enable the Infrared Endec before enabling the GPIO
Port alternate function for the corresponding pin.
To prevent spurious signals during IrDA data transmission, set the IREN bit in the
UART Control Register Definitions
Z8 Encore! XP
on page 100.
Product Specification
Infrared Encoder/Decoder
®
F0822 Series
112
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