ST72F63BK4M1 STMicroelectronics, ST72F63BK4M1 Datasheet - Page 137
![IC MCU 8BIT LS 16K 34-SOIC](/photos/12/15/121510/497-34-soic_series_sml.jpg)
ST72F63BK4M1
Manufacturer Part Number
ST72F63BK4M1
Description
IC MCU 8BIT LS 16K 34-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BK4M1
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
34-SOIC (7.5mm Width)
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SCI, USB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
27
Number Of Timers
2 x 16 bit
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit
For Use With
497-5521 - EVAL BOARD LOW SPEED USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-2115-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72F63BK4M1
Manufacturer:
ST
Quantity:
20 000
ST7263Bxx
Table 54.
Mnemo
JRUGT
JRULE
SWAP
PUSH
TRAP
NEG
NOP
RRC
XOR
MUL
POP
RCF
RSP
SBC
SRA
SUB
RET
RLC
SCF
SRL
TNZ
RIM
SLA
WFI
SIM
SLL
OR
LD
Instructions (continued)
Push onto the Stack
Shift right Arithmetic
Reset Stack Pointer
Test for Neg & Zero
Subtract with Carry
Jump if (C + Z = 0)
Jump if (C + Z = 1)
Negate (2's compl)
Pop from the Stack
Shift left Arithmetic
Subroutine Return
Rotate right true C
Disable Interrupts
Enable Interrupts
Rotate left true C
Wait for Interrupt
Reset carry flag
Shift right Logic
Shift left Logic
SWAP nibbles
No Operation
OR operation
Set carry flag
Exclusive OR
Description
Subtraction
S/W trap
Multiply
Load
Dst[7..4] <=> Dst[3..0]
Function/example
Dst7 => Dst => C
S = Max allowed
C <= Dst <= C
C => Dst => C
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
A = A XOR M
S/W interrupt
A = A - M - C
Unsigned <=
Unsigned >
X,A = X * A
A = A + M
dst <= src
A = A - M
neg $10
pop reg
pop CC
tnz lbl1
push Y
C = 1
C = 0
I = 0
I = 1
Doc ID 7516 Rev 8
A, X, Y
reg, M
reg, M
reg, M
reg, M
reg, M
reg, M
reg, M
reg, M
reg, M
Dst
reg
CC
M
A
A
A
A
reg, CC
X, Y, A
M, reg
Src
M
M
M
M
M
M
H
H
0
0
1
1
0
I
I
Instruction set
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
137/186
C
C
C
C
C
C
C
C
C
C
C
0
0
1