ST72F63BK4M1 STMicroelectronics, ST72F63BK4M1 Datasheet - Page 164
![IC MCU 8BIT LS 16K 34-SOIC](/photos/12/15/121510/497-34-soic_series_sml.jpg)
ST72F63BK4M1
Manufacturer Part Number
ST72F63BK4M1
Description
IC MCU 8BIT LS 16K 34-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BK4M1
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
34-SOIC (7.5mm Width)
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SCI, USB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
27
Number Of Timers
2 x 16 bit
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit
For Use With
497-5521 - EVAL BOARD LOW SPEED USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-2115-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72F63BK4M1
Manufacturer:
ST
Quantity:
20 000
Electrical characteristics
164/186
Figure 78. ADC accuracy characteristics
1. (1) Example of an actual transfer curve; (2) The ideal transfer curve; (3) End point correlation line.
2. E
E
E
E
E
line.
T
O
G
D
L
=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation
=Differential Linearity Error: maximum deviation between actual steps and the ideal one.
=Offset Error: deviation between the first actual transition and the first ideal one.
=Gain Error: deviation between the last ideal transition and the last actual one.
255
254
253
7
6
5
4
3
2
1
0
V
SSA
Digital Result ADCDR
1
1LSB
E
O
2
IDEAL
3
=
4
V
---------------------------------------- -
DDA
Doc ID 7516 Rev 8
5
256
1 LSB
–
V
E
SSA
6
T
IDEAL
E
7
L
(2)
E
D
253 254 255 256
(3)
(1)
E
G
V
DDA
V
in
(LSB
IDEAL
)
ST7263Bxx