ST72F63BK6M1 STMicroelectronics, ST72F63BK6M1 Datasheet - Page 122
![MCU 8BIT LS USB 32KB FLSH 34SOIC](/photos/12/15/121510/497-34-soic_series_sml.jpg)
ST72F63BK6M1
Manufacturer Part Number
ST72F63BK6M1
Description
MCU 8BIT LS USB 32KB FLSH 34SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BK6M1
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
34-SOIC (7.5mm Width)
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
19
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel / 8 bit, 12 Channel
For Use With
497-8428 - BOARD EVAL CHARGER ST7260/L6924D497-5521 - EVAL BOARD LOW SPEED USB497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5625-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
On-chip peripherals
122/186
I²C Clock Control register (CCR)
Reset value: 0000 0000 (00h)
FM/SM
7
[6:0] CC[6:0] 7-bit clock divider.
2 ARLO Arbitration lost.
1 BERR Bus error.
0 GCAL General Call (Slave mode).
7 FM/SM Fast/Standard I²C mode.
CC6
This bit is set and cleared by software. It is not cleared when the interface is
disabled (PE=0).
0: Standard I²C mode
1: Fast I²C mode
These bits select the speed of the bus (F
not cleared when the interface is disabled (PE=0).
Refer to the Electrical Characteristics section for the table of value.
Note: The programmed F
This bit is set by hardware when the interface loses the arbitration of the bus to
another master. An interrupt is generated if ITE=1. It is cleared by software reading
SR2 register or by hardware when the interface is disabled (PE=0).
After an ARLO event the interface switches back automatically to Slave mode
(M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Note: In a Multimaster environment, when the interface is configured in Master
This bit is set by hardware when the interface detects a misplaced Start or Stop
condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Note: If a Bus Error occurs, a Stop or a repeated Start condition should be
This bit is set by hardware when a general call address is detected on the bus while
ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when
the interface is disabled (PE=0).
0: No general call address detected on bus
1: general call address detected on bus
Receive mode it does not perform arbitration during the reception of the
Acknowledge Bit. Mishandling of the ARLO bit from the I2CSR2 register
may occur when a second master simultaneously requests the same data
from the same slave and the I
The ARLO bit is then left at 0 instead of being set.
generated by the Master to re-synchronize communication, get the
transmission acknowledged and the bus released for further communication
CC5
Doc ID 7516 Rev 8
CC4
SCL
Read/write
assumes no load on SCL and SDA lines.
CC3
2
C master does not acknowledge the data.
SCL
) depending on the I²C mode. They are
CC2
CC1
ST7263Bxx
CC0
0