STM32F103C6T7A STMicroelectronics, STM32F103C6T7A Datasheet - Page 63

MCU ARM 32BIT 32KB FLASH 48LQFP

STM32F103C6T7A

Manufacturer Part Number
STM32F103C6T7A
Description
MCU ARM 32BIT 32KB FLASH 48LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheets

Specifications of STM32F103C6T7A

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Featured Product
STM32 Cortex-M3 Companion Products
Eeprom Size
-
Cpu Family
STM32
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Interface Type
CAN/I2C/SPI/USART
Total Internal Ram Size
10KB
# I/os (max)
37
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
On-chip Adc
2(10-chx12-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
For Use With
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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STM32F103x4, STM32F103x6
5.3.16
Communications interfaces
I
Unless otherwise specified, the parameters given in
performed under the ambient temperature, f
conditions summarized in
The STM32F103xx performance line I
I
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and V
The I
injection characteristics
(SDA and SCL) .
Table 40.
1. Guaranteed by design, not tested in production.
2. f
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
2
2
t
C communication protocol with the following restrictions: the I/O pins SDA and SCL are
C interface characteristics
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
t
su(STO)
4 MHz to achieve fast mode I
maximum I2C fast mode clock.
period of SCL signal.
undefined region of the falling edge of SCL.
t
t
t
su(STA)
h(SDA)
PCLK1
r(SDA)
h(STA)
r(SCL)
f(SDA)
f(SCL)
C
2
C characteristics are described in
b
must be higher than 2 MHz to achieve standard mode I
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
Stop condition setup time
Stop to Start condition time
(bus free)
Capacitive load for each bus
line
I
2
C characteristics
Parameter
for more details on the input/output alternate function characteristics
Table
DD
2
C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz
is disabled, but is still present.
Doc ID 15060 Rev 5
9.
2
C interface meets the requirements of the standard
Standard mode I
Table
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
PCLK1
(3)
40. Refer also to
frequency and V
Table 40
2
1000
Max
300
400
C frequencies. It must be higher than
2
C
(1)
are derived from tests
20 + 0.1C
Fast mode I
Section 5.3.12: I/O current
Electrical characteristics
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
(4)
DD
supply voltage
b
2
C
900
Max
300
300
400
(1)(2)
(3)
Unit
μs
μs
pF
63/87
µs
ns
µs

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