ST72F321R6TC STMicroelectronics, ST72F321R6TC Datasheet - Page 187
ST72F321R6TC
Manufacturer Part Number
ST72F321R6TC
Description
IC MCU 8BIT 32K FLASH 64-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F321AR7T6.pdf
(193 pages)
Specifications of ST72F321R6TC
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Manufacturer
Quantity
Price
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Part Number:
ST72F321R6TC
Manufacturer:
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TNZ Y
jrne OUT
LD A,sema
edge is detected
CP A,#01
jrne OUT
call call_routine; call the interrupt routine
OUT:LD A,#00
LD sema,A
.call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt
LD A,#00
LD sema,A
IRET
Case 2: Writing to PxOR or PxDDR with Global In-
terrupts Disabled:
SIM
LD A,PFDR
AND A,#$02
LD X,A
PxOR/PxDDR
LD A,#$90
LD PFDDR,A; Write into PFDDR
LD A,#$ff
LD PFOR,A
LD A,PFDR
AND A,#$02
LD Y,A
PxDDR
LD A,X
cp A,#$02
jrne OUT
TNZ Y
jrne OUT
LD A,#$01
LD sema,A ; set the semaphore to '1' if edge is
detected
RIM
LD A,sema ; check the semaphore status
CP A,#$01
; set the interrupt mask
; store the level before writing to
; store the level after writing to PxOR/
; check for falling edge
; reset the interrupt mask
; check the semaphore status if
; entry to call_routine
; entry to interrupt routine
; Write to PFOR
jrne OUT
call call_routine; call the interrupt routine
RIM
OUT:
JP while_loop
.call_routine ; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt
LD A,#$00
LD sema,A
IRET
15.1.6
interrupt routine
When an active interrupt request occurs at the
same time as the related flag is being cleared, an
unwanted reset may occur.
Note: clearing the related interrupt mask will not
generate an unwanted reset
Concurrent interrupt context
The symptom does not occur when the interrupts
are handled normally, i.e.
when:
– The interrupt flag is cleared within its own inter-
– The interrupt flag is cleared within any interrupt
– The interrupt flag is cleared in any part of the
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
Perform SIM and RIM operation before and after
resetting an active interrupt request.
Example:
Nested interrupt context:
The symptom does not occur when the interrupts
are handled normally, i.e.
when:
– The interrupt flag is cleared within its own inter-
rupt routine
routine
code while this interrupt is disabled
rupt routine
SIM
reset interrupt flag
RIM
ST72321Rx ST72321ARx ST72321Jx
Clearing
RIM
; entry to interrupt routine
active
interrupts
outside
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