ST72F264G2B6 STMicroelectronics, ST72F264G2B6 Datasheet - Page 104
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ST72F264G2B6
Manufacturer Part Number
ST72F264G2B6
Description
MCU 8-BIT 8K FLASH 32-SDIP
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST72F264G2B6
Mfg Application Notes
ST7 Checksum Capability, AN1070 App Note
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SDIP (0.400", 10.16mm)
Processor Series
ST72F2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7F264-IND/USB, ST72F34X-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
For Use With
497-6423 - BOARD EVAL BASED ON ST72264G1497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5570
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F264G2B6
Manufacturer:
ST
Quantity:
10
Company:
Part Number:
ST72F264G2B6
Manufacturer:
NEC
Quantity:
6 097
Part Number:
ST72F264G2B6
Manufacturer:
ST
Quantity:
20 000
ST72260Gx, ST72262Gx, ST72264Gx
I
Acknowledge may be enabled and disabled by
software.
The I
dress can be selected by software.
The speed of the I
between Standard (up to 100KHz) and Fast I
(up to 400KHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 58. I
104/172
2
C BUS INTERFACE (Cont’d)
SCL or SCLI
SDA or SDAI
2
C interface address and/or general call ad-
2
C Interface Block Diagram
2
C interface may be selected
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
DATA CONTROL
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL REGISTER (CR)
2
C
The SCL frequency (F
grammable clock divider which depends on the
I
When the I
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
When the I
ports revert to being standard I/O port pins.
2
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
C bus mode.
DATA SHIFT REGISTER
DATA REGISTER (DR)
CONTROL LOGIC
COMPARATOR
INTERRUPT
2
2
C cell is disabled, the SDA and SCL
C cell is enabled, the SDA and SCL
scl
) is controlled by a pro-