ST72F264G2B6 STMicroelectronics, ST72F264G2B6 Datasheet - Page 106
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ST72F264G2B6
Manufacturer Part Number
ST72F264G2B6
Description
MCU 8-BIT 8K FLASH 32-SDIP
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST72F264G2B6
Mfg Application Notes
ST7 Checksum Capability, AN1070 App Note
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SDIP (0.400", 10.16mm)
Processor Series
ST72F2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7F264-IND/USB, ST72F34X-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
For Use With
497-6423 - BOARD EVAL BASED ON ST72264G1497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5570
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
ST72F264G2B6
Manufacturer:
ST
Quantity:
10
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Part Number:
ST72F264G2B6
Manufacturer:
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Part Number:
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ST72260Gx, ST72262Gx, ST72264Gx
I
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
SMBus Compatibility
ST7 I
supports all SMBus adressing modes, SMBus bus
protocols and CRC-8 packet error checking. Refer
to AN1713: SMBus Slave Driver For ST7 I
ripheral.
11.6.4.2 Master Mode
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condi-
tion.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the
Slave address, holding the SCL line low (see
Figure 59
Slave address transmission
Then the slave address is sent to the SDA line via
the internal shift register.
In 7-bit addressing mode, one address byte is
sent.
In 10-bit addressing mode, sending the first byte
including the header sequence causes the follow-
ing event:
– The EVF bit is set by hardware with interrupt
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register, holding
the SCL line low (see
quencing EV9).
106/172
2
C INTERFACE (Cont’d)
an interrupt if the ITE bit is set.
generation if the ITE bit is set.
2
C is compatible with SMBus V1.1 protocol. It
Transfer sequencing EV5).
Figure 59
Transfer se-
2
C Pe-
Then the second address byte is sent by the inter-
face.
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt
Then the master waits for a read of the SR1 regis-
ter followed by a write in the CR register (for exam-
ple set PE bit), holding the SCL line low (see
ure 59
Next the master must enter Receiver or Transmit-
ter mode.
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
sequence with the least significant bit set
(11110xx1).
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR reg-
ister via the internal shift register. After each byte
the interface generates in sequence:
– Acknowledge pulse if the ACK bit is set
– EVF and BTF bits are set by hardware with an in-
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see
quencing EV7).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to slave mode (M/SL bit
cleared).
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
generation if the ITE bit is set.
terrupt if the ITE bit is set.
Transfer sequencing EV6).
Figure 59
Transfer se-
Fig-