ST72F264G2B6 STMicroelectronics, ST72F264G2B6 Datasheet - Page 22
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ST72F264G2B6
Manufacturer Part Number
ST72F264G2B6
Description
MCU 8-BIT 8K FLASH 32-SDIP
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST72F264G2B6
Mfg Application Notes
ST7 Checksum Capability, AN1070 App Note
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SDIP (0.400", 10.16mm)
Processor Series
ST72F2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7F264-IND/USB, ST72F34X-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
For Use With
497-6423 - BOARD EVAL BASED ON ST72264G1497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5570
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F264G2B6
Manufacturer:
ST
Quantity:
10
Company:
Part Number:
ST72F264G2B6
Manufacturer:
NEC
Quantity:
6 097
Part Number:
ST72F264G2B6
Manufacturer:
ST
Quantity:
20 000
ST72260Gx, ST72262Gx, ST72264Gx
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
■
■
■
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in
■
■
■
The 4096 CPU clock cycle delay allows the oscil-
lator to stabilise and ensures that recovery has
taken place from the Reset state. The shorter or
longer clock cycle delay should be selected by op-
tion byte to correspond to the stabilization time of
the external oscillator used in the application.
Figure 12. Reset Block Diagram
22/172
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Active Phase depending on the RESET source
4096 CPU clock cycle delay (selected by option
byte)
RESET vector fetch
RESET
Figure
11:
V
Figure
DD
R
ON
12:
Filter
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 11. RESET Sequence Phases
6.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least t
order to be recognized (see
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
GENERATOR
PULSE
Active Phase
4096 CLOCK CYCLES
INTERNAL RESET
RESET
ON
weak pull-up resistor.
WATCHDOG RESET
LVD RESET
Figure
INTERNAL
RESET
13). This de-
VECTOR
h(RSTL)in
FETCH
in