ST72F264G2B6 STMicroelectronics, ST72F264G2B6 Datasheet - Page 75
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ST72F264G2B6
Manufacturer Part Number
ST72F264G2B6
Description
MCU 8-BIT 8K FLASH 32-SDIP
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST72F264G2B6
Mfg Application Notes
ST7 Checksum Capability, AN1070 App Note
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SDIP (0.400", 10.16mm)
Processor Series
ST72F2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7F264-IND/USB, ST72F34X-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
For Use With
497-6423 - BOARD EVAL BASED ON ST72264G1497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5570
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F264G2B6
Manufacturer:
ST
Quantity:
10
Company:
Part Number:
ST72F264G2B6
Manufacturer:
NEC
Quantity:
6 097
Part Number:
ST72F264G2B6
Manufacturer:
ST
Quantity:
20 000
11.4 SERIAL PERIPHERAL INTERFACE (SPI)
11.4.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
11.4.2 Main Features
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Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
Six master mode frequencies (f
f
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun
flags
CPU
/2 max. slave mode frequency (see note)
CPU
/4 max.)
11.4.3 General Description
Figure 46
(SPI) block diagram. There are 3 registers:
The SPI is connected to external devices through
4 pins:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
– SS: Slave select:
put by SPI slaves
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master
ST72260Gx, ST72262Gx, ST72264Gx
shows the serial peripheral interface
Device
.
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