STM32F103RBT7TR STMicroelectronics, STM32F103RBT7TR Datasheet - Page 30

• Manufacturer Part Number: STM32F103RBT7TR
• Description: MCU ARM 32BIT 64KB FLASH 64LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F103RBT7TR

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 51
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Processor Series: STM32F103x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 20 KB
• Interface Type: CAN, I2C, SPI, USART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, KSDK-STM32-PLUS, KSK-STM32-JL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ST-LINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel)
• For Use With: 497-10048 - BOARD EVAL ACCELEROMETER497-10030 - STARTER KIT FOR STM32KSDKSTM32-PL - KIT IAR KICKSTART STM32 CORTEXM3497-8512 - KIT STARTER FOR STM32F10XE MCU497-8511 - KIT STARTER FOR STM32 512K FLASH497-8505 - KIT STARTER FOR STM32F10XE MCU497-8418 - BOARD DEMO DGTL PHOTOFRAME STM32497-6438 - BOARD EVALUTION FOR STM32 512K497-6289 - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U - BOARD EVAL MCBSTM32 + ULINK2MCBSTM32 - BOARD EVAL FOR STM STM32X SER497-6053 - KIT STARTER FOR STM32497-6052 - KIT STARTER FOR STM32497-6050 - KIT STARTER FOR STM32497-6049 - KIT EVALUATION LOW COST STM32497-6048 - BOARD EVALUATION FOR STM32497-6047 - KIT DEVELOPMENT FOR STM32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Pinouts and pin description
Table 5.
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The V
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
9. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages, and C1 and C2 in the
30/92
D4
C4
E5
F5
number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1
and USART1 & USART2, respectively. Refer to
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be
remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no
need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the
STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
47
48
-
-
D4
E4
-
-
Pins
Medium-density STM32F103xx pin definitions (continued)
63
64 100 1
-
-
97
98
99 36
-
-
Pin name
V
V
PE0
PE1
DD_3
SS_3
Table 2 on page
Doc ID 13587 Rev 11
I/O FT
I/O FT
S
S
10.
(after reset)
function
V
V
Main
PE0
PE1
DD_3
SS_3
(3)
REF+
functionality is provided instead.
STM32F103x8, STM32F103xB
TIM4_ETR
Default
Alternate functions
Remap
(4)