Z86E4312FSC Zilog, Z86E4312FSC Datasheet
Z86E4312FSC
Specifications of Z86E4312FSC
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... Z86E33/733/E34 Z86E43/743/E44 ® CMOS Z8 OTP Microcontrollers Product Specification PS022901-0508 ® Copyright ©2008 by Zilog , Inc. All rights reserved. www.zilog.com ...
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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS022901-0508 ...
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Revision History Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below. Date Revision Level Description May 2008 01 PS022901-0508 ...
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Table of Contents Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Architectural Overview Zilog’s Z86E33/733/E34, E43/743/E44 8-Bit One-Time Programmable (OTP) Microcon- trollers are members of Zilog’s single-chip Z8 circuitry, programmable Watchdog Timers, Low Noise EMI options, and easy hardware/ software system expansion capability. Four basic address spaces support a wide range of memory configurations. The designer has access to three additional control registers that allow easy access to register mapped peripheral and I/O circuits ...
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Table 1. Z86E33/733/E34, E43/743/E44 Features (Continued) ROM Device (KB) Z86E44 16 1 General-Purpose • Standard Temperature (V • Extended Temperature (V • Available Packages: 28-Pin DIP/SOIC/PLCC OTP (E33/733/E34) – 40-Pin DIP OTP (E43/743/E44) – 44-Pin PLCC/LQFP OTP (E43/743/E44) – • ...
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On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive Functional Block Diagram Figure 1 displays the functional block diagram. Output Input Port 3 Counter/ TimerS (2) Interrupt Control Two Analog Comparators Port 2 I/O ...
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AD 11-0 Z8 MCU AD 13-0 Address Counter PGM + Test Mode Logic CLR CLK (P00) (P01) EPM PGM P32 P02 CE XT1 Figure 2. EPROM Programming Block Diagram PS022901-0508 CMOS Z8 D7-0 AD 11-0 Address MUX D7-0 EPROM TEST ...
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Pin Description R/W P25 P26 P27 P04 P05 P06 P14 P15 P07 V CC P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 AS Figure 3. 40-Pin DIP Pin Configuration Standard Mode Table 2. 40-Pin DIP Pin Identification Standard Mode Pin ...
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Table 2. 40-Pin DIP Pin Identification Standard Mode (Continued) Pin No Symbol 15 XTAL1 16-18 P31-P33 19 P34 RESET 22 P35 23 P37 24 P36 25 P30 26-27 P00-P01 28-29 P10-P11 30 P02 31 GND 32-33 P12-P13 ...
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P21 P22 P23 P24 DS NC R/W P25 P26 P27 P04 Figure 4. 44-Pin PLCC Pin Configuration Standard Mode Table 3. 44-Pin PLCC Pin Identification Pin No Symbol 1-2 GND 3-4 P12-P13 5 P03 6-10 P20-P24 ...
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Table 3. 44-Pin PLCC Pin Identification (Continued) Pin No Symbol 27 XTAL2 28 XTAL1 29-31 P31-P33 32 P34 R//RL 35 RESET 36 P35 37 P37 38 P36 39 P30 40-41 P00-P01 42-43 P10-P11 44 P02 PS022901-0508 ® ...
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P21 P22 P23 P24 DS NC R/W P25 P26 P27 P04 Figure 5. 44-Pin LQFP Pin Configuration Standard Mode Table 4. 44-Pin LQFP Pin Identification Pin No Symbol 1-2 P05-P06 3-4 P14-P15 5 P07 6 8-9 P16-P17 10 ...
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Table 4. 44-Pin LQFP Pin Identification (Continued) Pin No Symbol 18 RESET 19 P35 20 P37 21 P36 22 P30 23-24 P00-P01 25-26 P10-P11 27 P02 28-29 GND 30-31 P12-P13 32 P03 33-37 P20- R/W ...
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EPM Figure 6. 40-Pin DIP Pin Configuration EPROM Mode Table 5. 40-Pin DIP Package Pin Identification EPROM Mode Pin No ...
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Table 5. 40-Pin DIP Package Pin Identification EPROM Mode (Continued) Pin 32-34 35-39 40 PS022901-0508 Symbol Function /PGM Prog. Mode GND Ground NC No Connection D0-D4 Data 0,1,2,3 Connection ® CMOS Z8 OTP Microcontrollers Product ...
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Figure 7. 44-Pin PLCC Pin Configuration EPROM Programming Mode Table 6. 44-Pin PLCC Pin Configuration EPROM Programming Mode Pin No 1-2 3-5 6-10 11-13 14-16 17-22 23-24 25-27 28 ...
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Table 6. 44-Pin PLCC Pin Configuration EPROM Programming Mode (Continued) Pin No 32- 42-43 44 PS022901-0508 Symbol Function NC No Connection CLR Clear CLK Clock NC No Connection /PGM Prog. Mode ® CMOS Z8 OTP Microcontrollers Product Specification ...
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Figure 8. 44-Pin LQFP Pin Configuration EPROM Programming Mode Table 7. 44-Pin LQFP Pin Identification EPROM Programming Mode Pin No 1-5 6-7 8- 15-22 23 ...
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Table 7. 44-Pin LQFP Pin Identification EPROM Programming Mode (Continued) Pin No 33-37 38-40 41-43 44 PS022901-0508 Symbol Function D0-D4 Data 0,1,2,3 Connection D5-D7 Data 5,6 Connection ® CMOS Z8 OTP Microcontrollers Product Specification Direction Input/Output ...
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Figure 9. Standard Mode 28-Pin DIP/SOIC Pin Configuration Table 8. 28-Pin DIP/SOIC/PLCC Pin Identification Standard Mode Pin No 1-3 4 11-13 14- 19- 24-28 PS022901-0508 1 28 P25 27 P26 2 26 ...
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XTAL2 XTAL1 Figure 10. Standard Mode 28-Pin PLCC Pin Configuration Figure 11. EPROM Programming Mode 28-Pin DIP/SOIC Pin Configuration PS022901-0508 P05 P06 P07 P31 ...
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Figure 12. EPROM Programming Mode 28-Pin PLCC Pin Configuration Table 9. 28-Pin EPROM Pin Identification EPROM Mode Pin # 1-3 4 14- ...
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Electrical Characteristics Absolute Maximum Ratings Table 10. Absolute Maximum Ratings Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to V Voltage on V Pin with Respect Voltage on XTAL1, P32, P33 and ...
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Total power dissipation should not exceed 1.21 W for the package. Power dissipation is calculated as follows: Total Power Dissipation = Standard Test Conditions The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to ...
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DC Electrical Characteristics Table 11. DC Electrical Characteristics T Symbol Parameter Clock Input 3.5V CH High Voltage 5.5V V Clock Input 3.5V CL Low Voltage 5.5V V Input High 3.5V IH Voltage 5.5V V Input Low 3.5V ...
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Table 11. DC Electrical Characteristics T Symbol Parameter Comparator 3.5V OFFSET Input Offset 5.5V Voltage V Input Common 3.5V ICR Mode Voltage 5.5V Range I Input 3.5V IL Leakage 5.5V I Output 3.5V OL Leakage 5.5V I ...
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Table 11. DC Electrical Characteristics T Symbol Parameter Power-On Reset 3.5V POR 5.5V V Auto Reset Voltage LV Notes 1. The V voltage specification of 5.5 V guarantees 5.0 V ± 0.5 V and the V CC ...
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Table 12. DC Electrical Characteristics T Symbo l Parameter Output High 4.5V OH1 Voltage 5.5V V Output Low 4.5V OL Voltage Low EMI 5.5V Mode V Output Low 4.5V OL1 Voltage 5.5V V Output Low 4.5V OL2 ...
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Table 12. DC Electrical Characteristics T Symbo l Parameter Standby Current 4.5V CC2 STOP Mode 5.5V 4.5V 5.5V I Auto Latch Low 4.5V ALL Current 5.5V I Auto Latch High 4.5V ALH Current 5.5V T Power-On Reset ...
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R/W 12 Port0 Port1 (Read) Port1 DS (Write) Figure 14. External I/O or Memory Read/Write Timing (Z86E43/743/E44 Only) Table 13. DC Electrical Characteristics T No. Symbol Parameter 1 TdA(AS) Address Valid to AS Rise ...
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Table 13. DC Electrical Characteristics T No. Symbol Parameter 4 TwAS AS Low Width 5 TdAS(DS) Address Float to DS Fall 6 TwDSR DS (Read) Low Width 7 TwDSW DS (Write) Low Width 8 TdDSR(DR) DS Fail to Read Data ...
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Table 13. DC Electrical Characteristics T No. Symbol Parameter 18 TdDM(AS) DM Valid to AS Rise Delay 19 ThDS(AS) DS Valid to Address Valid Hold Time 3.5V Notes 1. The V voltage specification of 5.5 V guarantees 5.0 V ± ...
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Table 14. DC Electrical Characteristics T No. Symbol Parameter 10 TdDS(A) DS Rise to Address Active Delay 11 TdDS(AS) DS Rise to AS Fall Delay 12 TdR/W(AS) R/W Valid to AS Rise Delay 13 TdDS(R/W) DS Rise to R/W Not ...
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Clock TIN 4 6 IRQN 8 Clock Setup Stop Mode Recovery Source Table 15. Additional Timing Table (Divide-By-One Mode Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise & Fall Times 3 ...
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Table 15. Additional Timing Table (Divide-By-One Mode Symbol Parameter 5 TwTinH Timer Input High Width 6 TpTin Timer Input Period 7 TrTin, Timer Input Rise & Fall TfTin Timer 8A TwIL Int. Request Low Time 8B TwIL Int. ...
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Table 16. Additional Timing Table (Divide-By-One Mode Symbol Parameter 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer Input ...
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Handshake Timing Diagrams Data In Data In Data In Valid 1 DAV (Input) RDY (Output) Data Out 7 DAV (Output) RDY (Input) Table 17. Additional Timing Table (Divide by Two Mode Symbol Parameter 1 TpC Input Clock Period ...
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Table 17. Additional Timing Table (Divide by Two Mode Symbol Parameter 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer Input Period 3.5V 7 TrTin, Timer Input Rise & TfTin Fall Timer ...
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Table 18. Additional Timing Table (Divide by Two Mode Symbol Parameter 1 TpC Input Clock Period 3.5V 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 3.5V 4 TwTinL Timer Input Low Width 5 ...
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Table 18. Additional Timing Table (Divide by Two Mode Symbol Parameter 12 Twdt Watchdog Timer Delay Time Before Timeout Notes 1. The V voltage specification of 5.5 V guarantees 5.0 V ± 0.5 V and the V CC ...
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CLR Clear (active High). This pin resets the internal address counter at the High Level. CLK Address Clock. This pin is a clock input. The internal address counter increases by one for each clock cycle. Application Precaution The production test-mode ...
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The Z86E43/743/E44 does not reset WDTMR, SMR, P2M, and P3M registers on a Stop- Mode Recovery operation. ROMless (input, active Low). This pin, when connected to GND, disables the internal ROM and forces the device to function as a Z86C90/C89 ...
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MCU Open-Drain OEN Out 1.5 In Port 1 (P17-P10). Port 8-bit, bidirectional, CMOS-compatible port with multi- plexed Address (A7-A0) and Data (D7-D0) ports. These eight I/O lines can be pro- grammed as inputs or outputs or can ...
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Port 1 can be placed in the high-impedance state along with Port 0, AS, DS, and R/W, allowing the Z86E43/743/E44 to share common resources in multiprocessor and DMA applications. In ROM mode, Port 1 is defined as input after reset. ...
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In Handshake Mode, Port 3 lines P31 and P36 are used as handshake control lines. The handshake direction is determined by the configuration (input or output) assigned to bit 7 of Port 2 (see Figure MCU Open Drain Open Out ...
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P32 with reference to the voltage on P33. The analog function is enabled by setting the D1 of Port 3 Mode Register (P3M). The comparator output can be outputted from P34 and P37, respectively, by setting PCON register Bit ...
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MCU P30 R247 = P3M P31 (AN1 P32 (AN2) + P33 (REF) - From Stop-Mode Recovery Source PS022901-0508 CMOS Z8 Port 3 (I/O or Control) Auto Latch 500 kΩ P30 Data Latch IRQ3 0 = ...
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Table 19. Port 3 Pin Assignments Pin I/O CTC1 P30 IN P31 P32 IN P33 IN P34 OUT P35 OUT P36 OUT T OUT P37 OUT Comparator Inputs. Port 3, P31, and P32, each have a comparator ...
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Functional Description The MCU incorporates the following special functions to enhance the standard Z8 archi- tecture to provide the user with increased design flexibility. RESET. The device is reset in one of three ways: 1. Power-On Reset 2. Watchdog Timer ...
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ROM Module 65535 External ROM and RAM 4096/8192/16384 4095/8191/16383 On-Chip Location of First Byte of EPROM Instruction Executed After RESET 12 IRQ5 11 IRQ5 10 IRQ4 9 IRQ4 8 7 IRQ3 Interrupt Vector IRQ3 6 (Lower Byte) IRQ2 5 4 ...
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EPROM 65535 External Data Memory 4096 /8192/16384 4095 /8191/16383 Not Addressable 0 Register File. The register file consists of three I/O port registers, 236/125 general-pur- pose registers, 15 control and status registers, and three system configuration registers in the expanded ...
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R253 Default after RESET = 00h Expanded Register File (ERF). The register file has been expanded to allow for addi- tional system control registers, mapping of additional peripheral devices and input/output ports into the register address ...
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This upper nibble of the register file addresses provided by the register pointer specifies the active working-register group Expanded ...
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REGISTER POINTER Expanded Register Working Register Group Pointer Z8 Reg. File %FF %F0 %7F %0F %00 Notes Unknown † For ROMless condition: “10110110” * Will not be reset with a STOP-Mode ...
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RAM Protect. The upper portion of the RAM’s address spaces 80h to EFh (excluding the control registers) can be protected from reading and writing. This option can be selected during the EPROM Programming Mode. After this option is selected, the ...
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OSC ÷2 ÷16 Internal Clock External Clock Clock Logic ÷4 Internal Clock Gated Clock Triggered Clock T P31 IN Figure 27. Counter/Timer Block Diagram Interrupts. The MCU has six different interrupts from six different sources. The inter- rupts are maskable ...
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Global Interrupt Enable Interrupt Request Table 20. Interrupt Types, Sources, and Vectors Name Source IRQ0 DAV0, IRQ0 IRQ1 IRQ1 IRQ2 DAV2, IRQ2 IRQ3 IRQ3 1RQ4 T0 IRQ5 T1 PS022901-0508 IRQ0 IRQ2 IRQ1 Interrupt Edge Select ...
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When more than one interrupt is pending, priorities are resolved by a programmable prior- ity encoder that is controlled by the Interrupt Priority Register (IPR). An interrupt machine cycle is activated when an interrupt request is granted. Thus, disabling all ...
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XTAL1 C1 XTAL2 C2 Ceramic Resonator or Crystal C1 TYP * MHz * Typical value including pin parasitics Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used ...
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STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 microamperes or less. STOP Mode is terminated by one of the following resets: either by WDT ...
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Comparator Output Port 3 (D0). Bit 0 controls the comparator output in Port 3. A “1” in this location brings the comparator outputs to P34 and P37, and a “0” releases the Port to its standard I/O configuration. The default ...
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SMR (Fh Default setting after RESET ** Default setting after RESET and STOP-Mode Recovery Figure 31. Stop Mode Recovery Register (Write-Only Except Bit D7, Which Is Read-Only) SCLK/TCLK Divide-by-16 Select (D0). ...
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STOP mode when programmed as analog inputs. When the Stop Mode Recovery sources are selected in this register then SMR2 register bits D0, D1 must be set to zero. Note: If the Port 2 pin is configured as an ...
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Table 22. Stop Mode Recovery Source Stop Mode Recovery Delay Select (D5). The 5 ms RESET delay after Stop Mode Recov- ery ...
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Reset and initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT is driven either by an on-board RC oscilla- tor or an external oscillator from XTAL1 pin. The POR clock source ...
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WDT time-out in STOP Mode will not reset SMR,SMR2,PCON, Note: WDTMR, P2M, P3M, Ports 2 & 3 Data Registers, but will activate the T POR WDTMR Register Accessibility. The WDTMR register is accessible only during the first 60 internal system ...
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RESET 4 Clock Filter WDT Select (WDTMR) CLK Source Select (WDTMR) XTAL Internal RC OSC + WDT From STOP Mode Recovery Source STOP Delay Select (SMR) Auto Reset Voltage. An on-board Voltage Comparator checks that ...
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V 3.7 CC (Volts) 3.5 3.3 3.1 2.8 2.7 2.5 2.3 -60 -40 -20 Figure 35. Typical V PS022901-0508 CMOS Voltage vs. Temperature LV ® OTP Microcontrollers Product Specification 65 100 120 140 Temperature ...
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Z8 Control Register Diagrams Ordering Information PCON (FH) 00h Default Setting After Reset † Must be set to “1” for Z86E33/733/E34 Figure 36. Port Configuration Register (PCON) (Write Only) PS022901-0508 CMOS Z8 ...
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SMR (Fh Note: Note used in conjunction with SMR2 Source * Default setting after RESET ** Default setting after RESET and STOP-Mode Recovery Figure 37. Stop Mode Recovery Register (Write Only Except ...
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WDTMR ( Default setting after RESET Figure 38. Watchdog Timer Mode Register (Write Only) SMR (0F Note: Not used in conjunction with SMR ...
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R240 R241 Timer Default After Reset = 00h Figure 41. Timer Mode Register (F1 PS022901-0508 CMOS Z8 D0 Reserved (Must be 0) Figure 40. Reserved D0 ...
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R242 Figure 42. Counter/Timer 1 Register (F2 R243 PRE1 *Default After Reset Figure 43. Prescaler 1 Register (F3 R244 Figure 44. ...
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R245 PRE0 Figure 45. Prescaler 0 Register (F5 R246 P2M Default after Reset Figure 46. Port 2 Mode Register (F6 PS022901-0508 CMOS Count ...
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R247 P3M Default After Reset = 00h † Z86E33/733/E34 Must be 00 Figure 47. Port 3 Mode Register (F7 PS022901-0508 CMOS Port 2 Pull-Ups Open Drain 1 Port 2 Push-Pull ...
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R248 P01M Reset Condition = 0100 1101B For ROMless Condition = 1011 0110B † Z86E33/733/E34 Must Default after Reset Figure 48. Port 0 and 1 Mode Register (F8 PS022901-0508 CMOS ...
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R249 IPR Figure 49. Interrupt Priority Register (F9 R250 IRQ Default After Reset = 00h Figure 50. Interrupt Request Register (FA PS022901-0508 D0 Interrupt Group Priority 000 Reserved 001 C ...
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R251 IMR This option must be selected when ROM code is submitted for ROM Masking, otherwise this control bit is disabled permanently Figure 51. Interrupt Mask Register (FB R252 Flags Figure 52. Flag ...
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R253 Default After Reset = 00h Figure 53. Register Pointer (FD R254 SPH Default After Reset = 00h Figure 54. Stack Pointer High (FE R254 SPL Default After Reset = ...
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Package Information Figure 56. 40-PIN DIP Package Diagram Figure 57. 44-PIN LQFP Package Diagram PS022901-0508 ® CMOS Z8 OTP Microcontrollers Product Specification Electrical Characteristics 77 ...
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Figure 58. 28-Pin DIP Package Diagram Figure 59. 28-Pin SOIC Package Diagram PS022901-0508 ® CMOS Z8 OTP Microcontrollers Product Specification Electrical Characteristics 78 ...
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... Ordering Information Table 24.Ordering Information Product Z86E3312PSC Z86E3312SCC Z86E3312PSC Z86E3412PEC Z86E3412PSC Z86E3412SSC Z86E3412VSC Z86E4312FSC Z86E4312PSC Z86E4312VSC Z86E4412FSC Z86E4412PEC Z86E4412PSC Z86E4412VSC Z8673312PSC Z8673312SSC Z8673312VSC Z8674312FSC Z8674312PSC Z8674312VSC PS022901-0508 CMOS Z8 Speed (MHz) Package Type 12 PDIP 12 SOIC 12 PLCC 12 PDIP 12 PDIP 12 SOIC 12 PLCC 12 LQFP 12 PDIP ...
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... For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog’s Technical Support at http://support.zilog.com. PS022901-0508 ® ...