STR911FAM42X6 STMicroelectronics, STR911FAM42X6 Datasheet - Page 29
![MCU 256KB FLASH 96K RAM 80LQFP](/photos/12/33/123346/str911fam42x6_sml.jpg)
STR911FAM42X6
Manufacturer Part Number
STR911FAM42X6
Description
MCU 256KB FLASH 96K RAM 80LQFP
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet
1.STEVAL-IFW001V1.pdf
(102 pages)
Specifications of STR911FAM42X6
Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
40
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
Processor Series
STR911x
Core
ARM966E-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
96 KB
Interface Type
CAN, I2C, IrDA, SSP, UART, USB
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
STR9-COMSTICK, STR910-EVAL, STR91X-SK/HIT, STR91X-SK/IAR, STR91X-SK/KEI, STR91X-SK/RAI, STR9-DK/RAIS, STR91X-DK/IAR, STX-PRO/RAIS, STR912-D/RAIS, STR79-RVDK/CPP, STR79-RVDKCPP/9, STR79-RVDK, STR79-RVDK/9, STR9-RVDK/BAS, STR79-RVDK/UPG
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES497-5067 - BOARD EVAL FOR STR910 FAMILY497-5066 - KIT STARTER KEIL FOR STR910497-5065 - KIT STARTER IAR KICKSTART STR912497-5064 - KIT STARTER FOR STR910 FAMILY497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-6278
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
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STR911FAM42X6
Manufacturer:
ST
Quantity:
320
Company:
Part Number:
STR911FAM42X6
Manufacturer:
STMicroelectronics
Quantity:
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ST
Quantity:
20 000
STR91xFAxxx
3.15.2
3.15.3
3.15.4
Boundary scan
Standard JTAG boundary scan testing compliant with IEEE-1149.1 is available on the
majority of pins of the STR91xFA for circuit board test during manufacture of the end
product. STR91xFA pins that are not serviced by boundary scan are the following:
●
●
●
CPU debug
The ARM966E-S CPU core has standard ARM EmbeddedICE-RT logic, allowing the
STR91xFA to be debugged through the JTAG interface. This provides advanced debugging
features making it easier to develop application firmware, operating systems, and the
hardware itself. Debugging requires that an external host computer, running debug software,
is connected to the STR91xFA target system via hardware which converts the stream of
debug data and commands from the host system’s protocol (USB, Ethernet, etc.) to the
JTAG EmbeddedICE-RT protocol on the STR91xFA. These protocol converters are
commercially available and operate with debugging software tools.
The CPU may be forced into a Debug State by a breakpoint (code fetch), a watchpoint (data
access), or an external debug request over the JTAG channel, at which time the CPU core
and memory system are effectively stopped and isolated from the rest of the system. This is
known as Halt Mode and allows the internal state of the CPU core, memory, and peripherals
to be examined and manipulated. Typical debug functions are supported such as run, halt,
and single-step. The EmbeddedICE-RT logic supports two hardware compare units. Each
can be configured to be either a watchpoint or a breakpoint. Breakpoints can also be data-
dependent.
Debugging (with some limitations) may also occur through the JTAG interface while the CPU
is running full speed, known as Monitor Mode. In this case, a breakpoint or watchpoint will
not force a Debug State and halt the CPU, but instead will cause an exception which can be
tracked by the external host computer running monitor software. Data can be sent and
received over the JTAG channel without affecting normal instruction execution. Time critical
code, such as Interrupt Service Routines may be debugged real-time using Monitor Mode.
JTAG security bit
This is a non-volatile bit (Flash memory based), which when set will not allow the JTAG
debugger or JTAG programmer to read the Flash memory contents.
Using JTAG ISP, this bit is typically programmed during manufacture of the end product to
prevent unwanted future access to firmware intellectual property. The JTAG Security Bit can
be cleared only by a JTAG “Full Chip Erase” command, making the STR91xFA device blank
(except for programmed OTP bytes), and ready for programming again. The CPU can read
the status of the JTAG Security Bit, but it may not change the bit value.
JTAG pins JTCK, JTMS, JTDI, JTDO, JTRSTn, JRTCK
Oscillator input pins X1_CPU, X2_CPU, X1_RTC, X2_RTC
Tamper detect input pin TAMPER_IN (128-pin and 144-pin packages only)
Doc ID 13495 Rev 6
Functional overview
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