STR711FR2T6 STMicroelectronics, STR711FR2T6 Datasheet

IC MCU ARM7 TDMI 256K 64-LQFP

STR711FR2T6

Manufacturer Part Number
STR711FR2T6
Description
IC MCU ARM7 TDMI 256K 64-LQFP
Manufacturer
STMicroelectronics
Series
STR7r
Datasheet

Specifications of STR711FR2T6

Core Processor
ARM7
Core Size
32-Bit
Speed
66MHz
Connectivity
HDLC, I²C, SmartCard, SPI, UART/USART, USB
Peripherals
PWM, WDT
Number Of I /o
30
Program Memory Size
256KB (256K x 8 + 16K)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
STR711x
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
CAN/EMI/USB
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
30
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MCBSTR7, KSK-STR711-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
STR710-SK/HIT, STR711-SK/IAR, STR712-SK/IAR, STR71X-SK/RAIS, STX-PRO/RAIS, STX-RLINK, STR79-RVDK/CPP, STR79-RVDK, STR79-RVDK/UPG
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 12-bit
For Use With
MCBSTR7UME - MCBSTR7 + ULINK-ME DEV KITMCBSTR7 - BOARD EVAL STM STR71X SERIES497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU497-4550 - KIT IAR STARTER STR711/STR712
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-4513

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0
Features
February 2008
Core
– ARM7TDMI 32-bit RISC CPU
– 59 MIPS @ 66 MHz from SRAM
– 45 MIPS @ 50 MHz from Flash
Memories
– Up to 256 Kbytes Flash program memory
– 16 Kbytes Flash data memory
– Up to 64 Kbytes RAM
– External Memory Interface (EMI) for up to 4
– Multi-boot capability
Clock, reset and supply management
– 3.0 to 3.6V application supply and I/Os
– Internal 1.8V regulator for core supply
– Clock input from 0 to 16.5 MHz
– Embedded RTC osc. running from external
– Embedded PLL for CPU clock
– Realtime Clock for clock-calendar function
– 5 power saving modes: SLOW, WAIT,
Nested interrupt controller
– Fast interrupt handling with multiple vectors
– 32 vectors with 16 IRQ priority levels
– 2 maskable FIQ sources
Up to 48 I/O ports
– 30/32/48 multifunctional bidirectional I/Os
(10 kcycles endurance, 20 years retention
@ 85° C)
(100 kcycles endurance, 20 years
retention@ 85° C)
banks of SRAM, Flash, ROM
32 kHz crystal
LPWAIT, STOP and STANDBY modes
Up to 14 ports with interrupt capability
ARM7TDMI™ 32-bit MCU with Flash, USB, CAN
5 timers, ADC, 10 communications interfaces
Rev 12
Table 1.
Reference
STR71xF
5 Timers
– 16-bit watchdog timer
– 3 16-bit timers with 2 input captures, 2
– 16-bit timer for timebase functions
10 communications interfaces
– 2 I
– 4 UART asynchronous serial interfaces
– Smartcard ISO7816-3 interface on UART1
– 2 BSPI synchronous serial interfaces
– CAN interface (2.0B Active)
– USB Full Speed (12 Mbit/s) Device
– HDLC synchronous communications
4-channel 12-bit A/D converter
– Sampling frequency up to 1 kHz
– Conversion range: 0 to 2.5 V
Development tools support
– Atomic bit SET and RES operations
LFBGA64
LFBGA64 8 x 8 x 1.7
output compares, PWM and pulse counter
Function with Suspend and Resume
LQFP64
10 x 10
2
C interfaces (1 multiplexed with SPI)
STR710FZ1, STR710FZ2,
STR711FR0, STR711FR1, STR711FR2,
STR712FR0, STR712FR1, STR712FR2,
STR715FR0
Device summary
8 x 8 x 1.7
Root part number
LFBGA144 10 x 10 x 1.7
STR71xF
LQFP144
20 x 20
www.st.com
1/78
78

Related parts for STR711FR2T6

STR711FR2T6 Summary of contents

Page 1

ARM7TDMI™ 32-bit MCU with Flash, USB, CAN Features ■ Core – ARM7TDMI 32-bit RISC CPU – 59 MIPS @ 66 MHz from SRAM – 45 MIPS @ 50 MHz from Flash ■ Memories – 256 Kbytes Flash program ...

Page 2

Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

STR71xF 5 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

Introduction 1 Introduction This datasheet provides the STR71x pinout, ordering information, mechanical and electrical device characteristics. For complete information on the STR71x microcontroller memory, registers and peripherals. please refer to the STR71x reference manual. For information on programming, erasing and ...

Page 5

... ARM tools and software. Extensive tools support STMicroelectronics’ 32-bit, ARM core-based microcontrollers are supported by a complete range of high-end and low-cost development tools to meet the needs of application developers. This extensive line of hardware/software tools includes starter kits and complete development packages all tailored for ST’ ...

Page 6

System architecture 3 System architecture Package choice: low pin-count 64-pin or feature-rich 144-pin LQFP or BGA The STR71x family is available in 5 main versions. The 144-pin versions have the full set of all features including CAN, USB and External ...

Page 7

STR71xF Flexible power management To minimize power consumption, you can program the STR71x to switch to SLOW, WAIT, LPWAIT (low power wait), STOP or STANDBY mode depending on the current system activity in the application. Flexible clock control Two external ...

Page 8

System architecture Realtime clock (RTC) The RTC provides a set of continuously running counters driven by the 32 kHz external crystal. The RTC can be used as a general timebase or clock/calendar/alarm function. When the STR71x is in Standby mode ...

Page 9

STR71xF Figure 1. STR71x block diagram CK CKOUT RSTIN JTDI JTCK JTMS JTRST JTDO DBGRQS BOOTEN V18[1:0] V33[6:0] VSS[9:0] V18BKP AVDD AVSS STDBY RTCXTO RTCXTI WAKEUP 14 AF P0[15:0] P1[15:0] P2[15:0] *Flash ...

Page 10

System architecture 3.2 Related documentation Available from www.arm.com: ARM7TDMI Technical reference manual Available from http://www.st.com: STR71x Reference manual STR7 Flash programming manual AN1774 - STR71x Software development getting started AN1775 - STR71x Hardware development getting started AN1776 - STR71x Enhanced ...

Page 11

STR71xF 3.3 Pin description for 144-pin packages Figure 2. STR710 LQFP pinout P0.10/U1.RX/U1.TX/SCDATA RDn P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS V33 P2.0/CSn.0 P2.1/CSn.1 P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA P2.2/CSn.2 P2.3/CSn.3 P2.4/A.20 P2.5/A.21 P2.6/A.22 BOOTEN P2.7/A.23 P2.8 N.C. N.C. VSS V33 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 ...

Page 12

System architecture Table 3. STR710 BGA ball connections P0.10 P2.0 2 VSS RDn 3 V33 P0.9 4 P0.6 P0.7 5 A.19 WEn.1 6 P0.3 A.15 7 P0.2 P0.1 8 A.9 A.10 9 VSS V33 10 A.8 N.C. ...

Page 13

STR71xF Table 4. STR710 pin description Pin n° Pin name P0.10/U1.RX U1.TX/ I SC.DATA P0.11/BOOT I /U1. P0.12/SC.CLK I ...

Page 14

System architecture Table 4. STR710 pin description Pin n° Pin name 13 E3 P2.4/A.20 I P2.5/A.21 I P2.6/A.22 I BOOTEN P2.7/A.23 I P2.8 I N.C. ...

Page 15

STR71xF Table 4. STR710 pin description Pin n° Pin name 33IO-PLL SSIO-PLL DBGRQS CKOUT P0.15/ 47 ...

Page 16

System architecture Table 4. STR710 pin description Pin n° Pin name SS18 D.0 I D.1 I D.2 I D.3 I/O 65 M10 D.4 I/O 66 ...

Page 17

STR71xF Table 4. STR710 pin description Pin n° Pin name 83 H12 V S 33IO-PLL 84 H11 V S SSIO-PLL P1.7/T1.OCM 85 H10 I P1.8 I G12 N.C. 88 F12 P1.11/CANRX I/O ...

Page 18

System architecture Table 4. STR710 pin description Pin n° Pin name P1.13/HCLK/ 107 D10 I I0.SCL P1.14/HRXD/ 108 C11 I I0.SDA 109 B11 N.C. 110 B10 N.C. 111 C10 P1.15/HTXD I 112 A9 V ...

Page 19

STR71xF Table 4. STR710 pin description Pin n° Pin name P0.2/S0.SCLK 125 A7 I /I1.SCL P0.3/S0.SS/ 126 A6 I I1.SDA 127 C7 P0.4/S1.MISO I 128 SS18 129 ...

Page 20

System architecture Table 4. STR710 pin description Pin n° Pin name P0.8/U0.RX/ 143 C4 I U0.TX P0.9/U0.TX/ 144 B3 I BOOT.0 1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to ...

Page 21

STR71xF 3.4 Pin description for 64-pin packages Figure 3. STR712/STR715 LQFP64 pinout P0.10/U1.RX/U1.TX/SCDATA P0.11/U1.TX/BOOT.1 P0.12/SCCLK P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA 1) CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os VSS BOOTEN 7 ...

Page 22

System architecture Figure 4. STR711 LQFP64 pinout P0.10/U1.RX/U1.TX/SCDATA P0.11/U1.TX/BOOT.1 P0.12/SCCLK P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA Table 5. STR711 BGA ball connections A 1 P0.10 2 P0.9 3 P0.5 4 VSS18 5 P0.2 6 V33 7 VSS 8 P1.15 22/ VSS ...

Page 23

STR71xF Table 6. STR712/715 BGA Ball Connections A 1 P0.10 P0.11 2 P0.9 3 P0.5 4 VSS18 5 P0.2 6 V33 7 VSS 8 P1.15 P1.14 1) CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os. ...

Page 24

System architecture Table 7. STR711/STR712/STR715 pin description Pin n° Pin name P0.10/U1.RX U1.TX/ I/O pd SC.DATA P0.11/BOOT I/O pd /U1. P0.12/SC.CLK I P0.13/U2.RX I/O pu T2.OCMPA ...

Page 25

STR71xF Table 7. STR711/STR712/STR715 pin description Pin n° Pin name P0.15 WAKEUP 21 G3 RTCXTI 22 H4 RTCXTO I STDBY 24 G4 RSTIN SSBKP 18BKP ...

Page 26

System architecture Table 7. STR711/STR712/STR715 pin description Pin n° Pin name P1.5/T1.ICAP P1.6/T1.OCM 33IO-PLL SSIO-PLL P1.7/T1.OCM ...

Page 27

STR71xF Table 7. STR711/STR712/STR715 pin description Pin n° Pin name P0.0/S0.MISO 52 B7 I/O pu /U3.TX P0.1/S0.MOSI 53 B6 I/O pu /U3.RX P0.2/S0.SCLK 54 A5 I/O pu /I1.SCL P0.3/S0.SS/ I/O pu .SDA 56 B5 P0.4/S1.MISO I ...

Page 28

System architecture Table 7. STR711/STR712/STR715 pin description Pin n° Pin name P0.8/U0.RX I/O pd 0.TX P0.9/U0.TX I/O pd OOT.0 1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to The Port ...

Page 29

STR71xF 3.6 I/O port configuration Table 8. Port bit configuration table Configuration Mode TTL Input Floating CMOS Input Floating CMOS Input Pull-Down (IPUPD) INPUT CMOS Input Pull-Up (IPUPD) Analog input Output Open-Drain Output Push-Pull OUTPUT Alternate Function Open-Drain CMOS floating ...

Page 30

System architecture 3.7 Memory mapping Figure 6. Memory map Addressable Memory Space 4 Gbytes 0xFFFF FFFF EIC 0xFFFF F800 7 APB2 0xE000 0000 6 APB1 0xC000 0000 5 PRCCU 0xA000 0000 4 Reserved 0x8000 0000 3 EXTMEM See Figure 8 ...

Page 31

STR71xF Figure 7. Mapping of Flash memory versions FLASH Memory Space 64 Kbytes + 16K RWW + regs 0x4010 DFBF FLASH Registers 0x4010 0000 reserved 0x400C 4000 B1F1 0x400C 2000 B1F0 0x400C 0000 reserved 0x4004 0000 reserved 0x4003 0000 reserved ...

Page 32

System architecture Figure 8. External memory map Addressable Memory Space 0xFFFF FFFF 0xFFFF F800 7 0xE000 0000 6 0xC000 0000 5 0xA000 0000 4 0x8000 0000 3 0x6000 0000 2 0x4000 0000 1 0x2000 0000 0 0x0000 0000 32/78 4 ...

Page 33

STR71xF 4 Electrical parameters 4.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 4.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage ...

Page 34

Electrical parameters 4.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure ...

Page 35

STR71xF Table 11. Current characteristics Symbol I Total current into V V33 I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin Injected ...

Page 36

Electrical parameters 4.3 Operating conditions Subject to general operating conditions for V Table 13. General operating conditions Symbol Internal CPU Clock f MCLK frequency Internal APB Clock f PCLK frequency Standard Operating V 33 Voltage (includes V V Backup Operating ...

Page 37

STR71xF 4.3.1 Supply current characteristics The current consumption is measured as described in on page 33. Total current consumption The MCU is placed under the following conditions: ● All I/O pins in input mode with a static value at V ...

Page 38

Electrical parameters Table 16. Typical power consumption data Symbol Parameter All periphs ON RUN mode current from RAM All periphs OFF I DDRUN All periphs ON RUN mode current from FLASH All periphs OFF I SLOW mode current DDSLOW WAIT ...

Page 39

STR71xF Figure 11. STOP I vs 100 3.1 3.2 3.3 V33 (V) Figure 13. WFI I vs 100 ...

Page 40

Electrical parameters On-chip peripherals Table 17. Peripheral current consumption Symbol I PLL1 supply current DD(PLL1) I PLL2 supply current DD(PLL2) I TIM Timer supply current DD(TIM) I BSPI supply current DD(BSPI) I UART supply current DD(UART) I I2C supply current ...

Page 41

STR71xF 4.3.2 Clock and timing characteristics External clock sources Subject to general operating conditions for V Table 18. CK external clock characteristics Symbol External clock source f CK frequency CK input pin high level V CKH voltage CK input pin ...

Page 42

Electrical parameters Table 19. RTCXT1 external clock characteristics Symbol External clock source f RTCXT1 frequency RTCXT1 input pin high level V RTCXT1H voltage RTCXT1 input pin low level V RTCXT1L voltage t w(RTCXT1) RTCXT1 high or low time t w(RTCXT1) ...

Page 43

STR71xF OSC32K crystal / ceramic resonator oscillator The STR7 RTC clock can be supplied with a 32 kHz Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the ...

Page 44

Electrical parameters Figure 16. RTC crystal oscillator and resonator PLL electrical characteristics V = 3.0 to 3.6V Table 21. PLL1 characteristics Symbol f PLL multiplier output clock PLLCLK1 PLL input clock f PLL1 PLL input clock duty cycle ...

Page 45

STR71xF Table 22. PLL2 characteristics Symbol PLL multiplier output f PLLCLK2 clock f PLL input clock PLL2 t PLL lock time LOCK2 ∆t PLL jitter (peak to peak) JITTER2 Table 23. Low-power mode wakeup timing Symbol t Wakeup from LPWFI ...

Page 46

Electrical parameters 4.3.3 Memory characteristics Flash memory V = 3.0 to 3.6V Table 24. Flash memory characteristics Symbol t Word Program PW t Double Word Program PDW t Bank 0 Program (256K) PB0 t Bank 1 Program (16K) ...

Page 47

STR71xF 4.3.4 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electro magnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by ...

Page 48

Electrical parameters Table 25. EMS data Symbol Voltage limits to be applied on any I/O pin V FESD to induce a functional disturbance Fast transient voltage burst limits applied through 100pF on V EFTB pins to induce ...

Page 49

... Static latch-up class DLU Dynamic latch-up class 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). ...

Page 50

Electrical parameters 4.3.5 I/O port pin characteristics General characteristics Subject to general operating conditions for V unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down ...

Page 51

STR71xF Figure 17. R vs. V with 0.0 -50.0 -100.0 -150.0 -200.0 -250.0 3 3.1 3.2 3.3 V33 (V) Figure 19. R vs. V with 300.0 250.0 200.0 150.0 100.0 50.0 0.0 3 3.1 ...

Page 52

Electrical parameters Output driving current Subject to general operating conditions for V Table 30. Output driving current I/O Symbol Type Output low level voltage for an I/O pin when 8 pins are sunk at same time Output ...

Page 53

STR71xF Figure 21. Typical V 3.09 3.08 3.07 3.06 3.05 3.04 3.03 3.02 3.01 -4 and =3.3V (high current ports 0.16 TA=-45°C TA=0°C 0.14 TA=+25°C TA=+90°C 0.12 0.10 0.08 0.06 0.04 0.02 0.00 -8 ...

Page 54

Electrical parameters Figure 22. Typical V vs 0.16 0.14 0.12 0.10 0.08 TA=-45°C TA=0°C 0.06 TA=+25°C TA=+90°C 0.04 0.02 0.00 3 3.1 3.2 3.3 V33 (V) Figure 23. Typical V vs 3.60 3.40 3.20 3.00 2.80 ...

Page 55

STR71xF RSTIN pin The RSTIN pin input driver is CMOS. A permanent pull-up is present which is the same (seeTable 29 on page PU Subject to general operating conditions for V Table 31. RESET pin characteristics Symbol ...

Page 56

Electrical parameters 4.3.6 TIM timer characteristics Subject to general operating conditions for V specified. Refer to the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). Table 32. TIM characteristics Symbol t Input capture pulse time w(ICAP)in ...

Page 57

STR71xF Table 34. EMI read operation Symbol t Read to CSn Removal Time RCR t Read Pulse Time RP t Read Data Setup Time RDS t Read Data Hold Time RDH t Read Address Setup Time RAS t Read Address ...

Page 58

Electrical parameters Figure 25. Read cycle timing: 16-bit read on 16-bit memory A[23:0] RDn CSn.x WEn.x D[15:0] (Input) Figure 26. Read cycle timing: 32-bit read on 16-bit memory A[23:0] RDn CSn.x WEn.x D[15:0] (Input) See Table 34 for read timing ...

Page 59

STR71xF Figure 28. Read cycle timing: 32-bit read on 8-bit memory A[23:0] RDn CSn.x WEn.x D[7:0] (Input) See Table 34 for read timing data. Figure 29. Write cycle timing: 16-bit write on 16-bit memory A[23:0] RDn CSn.x WEn.x D[15:0] (Output) ...

Page 60

Electrical parameters Figure 31. Write cycle timing: 16-bit write on 8-bit memory A[23:0] RDn CSn.x WEn.x D[7:0] (Output) Figure 32. Write cycle timing: 32-bit write on 8-bit memory A[23:0] RDn CSn.x WEn.x t D[7:0] (Output) See Table ...

Page 61

STR71xF Table 36. I2C characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) SDA and SCL rise time t r(SCL) t f(SDA) ...

Page 62

Electrical parameters Figure 33. Typical application with BUS SDA t f(SDA) SCL t h(STA) Table 37. SCL Frequency Table ( Legend External pull-up resistance speed SCL NA = ...

Page 63

STR71xF 4.3.9 BSPI - buffered serial peripheral interface Subject to general operating conditions for V Refer to I/O port pin characteristics on page 50 function characteristics (SS, SCK, MOSI, MISO). Table 38. BSPI characteristics Symbol Parameter f SCK SPI clock ...

Page 64

Electrical parameters Figure 34. SPI slave timing diagram with CPHA=0 SS INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 MISO OUTPUT MOSI INPUT Figure 35. SPI slave timing diagram with CPHA=1 SS INPUT CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO OUTPUT MOSI INPUT Figure 36. ...

Page 65

STR71xF 4.3.10 USB characteristics The USB interface is USB-IF certified (Full Speed). Table 39. USB startup time Symbol t STARTUP Table 40. USB DC characteristics Symbol V Differential Input Sensitivity DI Differential Common Mode V CM Single Ended Receiver V ...

Page 66

Electrical parameters 4.3.11 ADC characteristics Subject to general operating conditions for AV Table 42. ADC characteristics Symbol Modulator Oversampling f MOD frequency V Conversion voltage range AIN Negative input leakage current on I lkg analog pins PBR Passband Ripple SINAD ...

Page 67

STR71xF Table 43. ADC accuracy with f Symbol Parameter ADC_DATA(0V) Converted code when AIN=0V ADC_DATA(2.5V) Converted code when AIN=2.5V Center voltage of Sigma-Delta VCM 1) Modulator TUE Total unadjusted error |E | Differential linearity error Integral linearity ...

Page 68

Electrical parameters Analog power supply and reference pins The AV and AV DD the high and low reference voltages for the conversion. Separation of the digital and analog power pins allow board designers to improve A/D performance. Conversion accuracy can ...

Page 69

STR71xF 5 Package characteristics 5.1 Package mechanical data Figure 40. 64-Pin low profile quad flat package (10x10 Recommended footprint (dimensions in mm) 1 Package characteristics mm inches Dim. Min Typ Max ...

Page 70

Package characteristics Figure 41. 144-Pin low profile quad flat package 108 109 b 144 Jedec Ref. MS-026-BFB 70/ Seating Plane Recommended footprint (dimensions in mm) ...

Page 71

STR71xF Figure 42. 64-Low profile fine pitch ball grid array package Figure 43. 144-low profile fine pitch ball grid array package Figure 44. Recommended PCB design rules (0.80/0.75mm pitch BGA) Dpad Dpad Dsm Solder paste – Non solder mask defined ...

Page 72

Package characteristics 5.2 Thermal characteristics The average chip-junction temperature, T following equation: Where: is the Ambient Temperature in °C, ● Θ is the Package Junction-to-Ambient Thermal Resistance, in °C/W, ● JA ● the sum of P ...

Page 73

STR71xF 6 Product history There are three versions of the STR710F series products. All versions are functionally identical and differ only with the points listed below. Version "A" was the first version produced and delivered. Version "Z" was the second ...

Page 74

Product history Figure 47. BGA144 STR710 version “Z” R710Z2H6 2208JVG Z MLT 22 551 Table 45 and X version differences Feature ARM7TDMI core device Identification (ID) code register (see ARM7TDMI Technical Reference Manual) Low power mode consumption in ...

Page 75

STR71xF 7 Ordering information Figure 49. STR71xF ordering information scheme Example: Product class STR71x microcontroller Peripheral set 0 = full peripheral set EMI, no CAN EMI, no USB EMI, no USB, ...

Page 76

Revision history 8 Revision history Table 46. Document revision history Date 17-Mar-2004 05-Apr-2004 08-Apr-2004 15-Apr-2004 7-Jul-2004 29-Oct-2004 25-Jan-2005 19-Apr-2005 13-Oct-2005 76/78 Revision 1 First Release 2 Updated “Electrical parameters” on page 33 2.1 Corrected STR712F Pinout. Pins 43/42 swapped. 2.2 ...

Page 77

STR71xF Table 46. Document revision history (continued) Date 22-May-2006 01-Aug-2006 06-Nov-2006 20-Mar-2007 13-Feb-2008 Revision Added Flashless device. Changed reset state of pins P1.10 and P1.13 from pu to pd, P0.15 from pu to floating and removed x in interrupt column ...

Page 78

... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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