ST10F272M-4TR3 STMicroelectronics, ST10F272M-4TR3 Datasheet - Page 54
ST10F272M-4TR3
Manufacturer Part Number
ST10F272M-4TR3
Description
MCU 16BIT 256K FLASH 144-LQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F272M-4TR3.pdf
(176 pages)
Specifications of ST10F272M-4TR3
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-MQFP, 144-PQFP
Processor Series
ST10F27x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
ST10F272M-4TR3
Manufacturer:
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Quantity:
10 000
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Interrupt system
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available vector. If more than one source is enabled to issue the request, the service routine
will have to take care to identify the real event to be serviced. This can easily be done by
checking the flag bits (byte low of XIRxSEL register). Note that the flag bits can also provide
information about events which are not currently serviced by the interrupt controller (since
they are masked through the enable bits), allowing an effective software management even
if the related interrupt request cannot be served: A periodic polling of the flag bits may be
implemented inside the user application.
Figure 9.
Table 30
X-interrupt vectors.
Table 30.
CAN1 interrupt
CAN2 interrupt
I
I
I
SSC1 receive
SSC1 transmit
SSC1 error
ASC1 receive
ASC1 transmit
ASC1 transmit buffer
ASC1 error
PLL unlock/OWD
PWM1 channel 3...0
2
2
2
C receive
C transmit
C error
IT source 7
IT source 6
IT source 5
IT source 4
IT source 3
IT source 2
IT source 1
IT source 0
summarizes the mapping of the different interrupt sources which shares the four
Interrupt source
X-interrupt basic structure
X-interrupt detailed mapping
15
7
Enable[7:0]
Flag[7:0]
0
8
XIRxSEL[7:0] (x = 0, 1, 2, 3)
XIRxSEL[15:8] (x = 0, 1, 2, 3)
XP0INT
x
x
x
x
x
x
x
x
XP1INT
x
x
x
x
x
x
x
x
XPxIC.XPxIR (x = 0, 1, 2, 3)
XP2INT
x
x
x
x
x
x
x
x
ST10F272M
XP3INT
x
x
x
x
x
x
x
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