ST10F272M-4TR3 STMicroelectronics, ST10F272M-4TR3 Datasheet - Page 89
ST10F272M-4TR3
Manufacturer Part Number
ST10F272M-4TR3
Description
MCU 16BIT 256K FLASH 144-LQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F272M-4TR3.pdf
(176 pages)
Specifications of ST10F272M-4TR3
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-MQFP, 144-PQFP
Processor Series
ST10F27x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10F272M-4TR3
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST10F272M
20.5
Watchdog timer reset
When the watchdog timer is not disabled during the initialization, or serviced regularly
during program execution, it will overflow and trigger the reset sequence.
Unlike hardware and software resets, the watchdog reset completes a running external bus
cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after
the programmed wait states.
When READY is sampled inactive (high) after the programmed wait states the running
external bus cycle is aborted. Then the internal reset sequence is started.
Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared
(that is written at ‘1’).
A Watchdog reset is always taken as synchronous: there is no influence on watchdog reset
behavior with RPD status. In case bidirectional reset is selected, a watchdog reset event
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though bidirectional reset is selected.
Refer to figures
bidirectional.
Figure 25. SW/WDT unidirectional reset (EA = 1)
P0[15:13]
RSTOUT
IBUS-CS
(internal)
FLARST
P0[12:8]
P0[7:2]
P0[1:0]
RSTIN
RST
25
and
26
for unidirectional SW reset timing, and to figures 27,
1024 TCL
Not transparent
Not transparent
Not transparent
Transparent
≤ 1ms
≤ 2 TCL
Not t.
Not t.
7 TCL
System reset
28
and
29
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