ST10F272M-4T3 STMicroelectronics, ST10F272M-4T3 Datasheet - Page 115
ST10F272M-4T3
Manufacturer Part Number
ST10F272M-4T3
Description
MCU 16BIT 256K FLASH 144-LQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F272M-4TR3.pdf
(176 pages)
Specifications of ST10F272M-4T3
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-MQFP, 144-PQFP
Processor Series
ST10F27x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
ST10F272M-4T3
Manufacturer:
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Quantity:
10 000
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ST10F272M
1. The system configuration is selected during reset. SYSCON reset value is 0000 0xx0 x000 0000b.
2.
3. The XPnIC interrupt control registers control interrupt requests from integrated X-bus peripherals. Some software
23.2
The following table lists all X-bus registers which are implemented in the ST10F272M ordered by their
name.
Note:
Table 46.
CAN1BRPER
CAN1BTR
CAN1CR
CAN1EC
CAN1IF1A1
CAN1IF1A2
CAN1IF1CM
CAN1IF1CR
CAN1IF1DA1
CAN1IF1DA2
CAN1IF1DB1
CAN1IF1DB2
CAN1IF1M1
CAN1IF1M2
CAN1IF1MC
CAN1IF2A1
CAN1IF2A2
CAN1IF2CM
CAN1IF2CR
CAN1IF2DA1
CAN1IF2DA2
CAN1IF2DB1
CAN1IF2DB2
CAN1IF2M1
CAN1IF2M2
controlled interrupt requests may be generated by setting the XPnIR bits (of XPnIC register) of the unused X-peripheral
nodes.
Reset value depends on different triggered reset event.
Name
X-registers
The X-Registers are not bit-addressable.
List of X-bus registers
Physical address
EF0Ch
EF1Ah
EF1Eh
EF1Ch
EF4Ah
EF4Eh
EF06h
EF00h
EF04h
EF18h
EF12h
EF10h
EF20h
EF22h
EF24h
EF14h
EF16h
EF48h
EF42h
EF40h
EF50h
EF52h
EF54h
EF44h
EF46h
CAN1: BRP extension register
CAN1: Bit timing register
CAN1: CAN control register
CAN1: Error counter
CAN1: IF1 arbitration 1
CAN1: IF1 arbitration 2
CAN1: IF1 command mask
CAN1: IF1 command request
CAN1: IF1 data A 1
CAN1: IF1 data A 2
CAN1: IF1 data B 1
CAN1: IF1 data B 2
CAN1: IF1 mask 1
CAN1: IF1 mask 2
CAN1: IF1 message control
CAN1: IF2 arbitration 1
CAN1: IF2 arbitration 2
CAN1: IF2 command mask
CAN1: IF2 command request
CAN1: IF2 data A 1
CAN1: IF2 data A 2
CAN1: IF2 data B 1
CAN1: IF2 data B 2
CAN1: IF2 Mask 1
CAN1: IF2 mask 2
Description
Reset value
Register set
FFFFh
FFFFh
FFFFh
FFFFh
0000h
2301h
0001h
0000h
0000h
0000h
0000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0001h
0000h
0000h
0000h
0000h
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