ST10F276Z5T3 STMicroelectronics, ST10F276Z5T3 Datasheet

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... Two 16-channel capture / compare units Table 1. Device summary Order code Package ST10F276Z5Q3 PQFP144 ST10F276Z5T3 LQFP144 December 2007 16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM ■ 4-channel PWM unit + 4-channel XPWM ■ A/D converter – ...

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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST10F276Z5 4.5.7 4.5.8 4.5.9 4.5.10 4.5.11 4.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 5.6 Alternate boot mode (ABM ...

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ST10F276Z5 12.2.1 12.2.2 12.3 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 20.2.1 20.2.2 20.3 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST10F276Z5 23.7.4 23.7.5 23.7.6 23.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 25 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST10F276Z5 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables Table 49. GPT2 timer input frequencies, resolutions and periods at 40 MHz Table 50. GPT2 timer input frequencies, ...

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ST10F276Z5 Table 102. 32 kHz Oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures List of figures Figure 1. Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST10F276Z5 Figure 49. Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Description 1 Description The ST10F276Z5 is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance ( million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL. The ST10F276Z5 is processed in 0.18 µ ...

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ST10F276Z5 restrictions and functional differences due to the XBUS peculiarities are present between the classic PWM, and the new XPWM. 2 ● interface on the XBUS is added (see X-I ● CLKOUT function can output either the ...

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Description Figure 1. Logic symbol 16/239 XTAL1 XTAL2 XTAL3 XTAL4 RSTIN RSTOUT V AREF V ST10F276Z5 AGND NMI STBY READY ALE WRL Port 5 16-bit ST10F276Z5 Port 0 ...

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ST10F276Z5 2 Pin data Figure 2. Pin configuration (top view) P6.0 / CS0 P6.1 / CS1 P6.2 / CS2 P6.3 / CS3 P6.4 / CS4 P6.5 / HOLD / SCLK1 P6.6 / HLDA / MTSR1 P6.7 / BREQ / MRST1 ...

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Pin data Table 2. Pin description Symbol Pin Type I ... ... 5 O P6 I/O 9-16 I/O I ... ... I/O P8.0 ...

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ST10F276Z5 Table 2. Pin description (continued) Symbol Pin Type 19-26 I P7.0 - P7.7 ... ... I/O ... ... 26 I/O 27-36 I 39- P5 P5.10 - P5.15 ...

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Pin data Table 2. Pin description (continued) Symbol Pin Type 65-70, I/O 73-80, I P3 P3.6 - P3.13, P3. ...

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ST10F276Z5 Table 2. Pin description (continued) Symbol Pin Type 85-92 I P4.0 –P4 ...

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Pin data Table 2. Pin description (continued) Symbol Pin Type STBY P0L.0 -P0L.7, 100-107, P0H.0 108, I/O P0H.1 - P0H.7 111-117 118-125 I/O 128-135 P1L.0 - P1L.7 P1H.0 - P1H.7 132 I 133 I 134 ...

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ST10F276Z5 Table 2. Pin description (continued) Symbol Pin Type XTAL1 138 I XTAL2 137 O XTAL3 143 I XTAL4 144 O RSTIN 140 I RSTOUT 141 O NMI 142 AREF AGND RPD 84 ...

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Functional description 3 Functional description The ST10F276Z5 architecture combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of ...

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ST10F276Z5 4 Internal Flash memory 4.1 Overview The on-chip Flash is composed by two matrix modules each one containing one array divided in two banks that can be read and modified independently one of the other: one bank can be ...

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Internal Flash memory 4.2.2 Modules structure The IFLASH module is composed by 2 banks. Bank 0 contains 384 Kbyte of program memory divided in 10 sectors. Bank 0 contains also a reserved sector named test-Flash. Bank 1 contains 128 Kbyte ...

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ST10F276Z5 Table 5. Flash modules sectorization (write operations or with roms1=’1’) Bank Bank 0 Test-Flash (B0TF) Bank 0 Flash 0 (B0F0) Bank 0 Flash 1 (B0F1) Bank 0 Flash 2 (B0F2) Bank 0 Flash 3 (B0F3) B0 Bank 0 Flash ...

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Internal Flash memory Table 6. Control register interface Bank FCR1-0 Flash control registers 1-0 FDR1-0 Flash data registers 1-0 FAR Flash address registers FER Flash error register Flash non volatile protection FNVWPXR X register Flash non volatile protection FNVWPIR I ...

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ST10F276Z5 Bank, or from the other module or again from another memory (internal RAM or external memory). Note: During a Write operation, when bit LOCK of FCR0 is set forbidden to write into the Flash Control Registers. 4.3.1 ...

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Internal Flash memory Table 7. Flash control register 0 low (continued) Bit Flash registers access locked When this bit is set, it means that the access to the Flash Control Registers FCR0H/- FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by ...

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ST10F276Z5 Table 8. Flash control register 0 high (continued) Bit Sector erase This bit must be set to select the Sector Erase operation in the Flash modules. The Sector Erase operation allows to erase all the Flash locations to 0xFF. ...

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Internal Flash memory 4.4.3 Flash control register 1 low The Flash control register 1 low (FCR1L), together with Flash control register 1 high (FCR1H), is used to select the sectors to erase, or during any write operation to monitor the ...

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ST10F276Z5 4.4.4 Flash control register 1 high The Flash control register 1 high (FCR1H), together with Flash control register 1 low (FCR1L), is used to select the sectors to erase, or during any write operation to monitor the status of ...

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Internal Flash memory Table 11. Banks (BxS) and sectors (BxFy) status bits meaning ERR SUSP 4.4.5 Flash data register 0 low The Flash address registers (FARH/L) and the Flash data registers (FDR1H/L-FDR0H/L) are used ...

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ST10F276Z5 4.4.7 Flash data register 1 low FDR1L (0x0E 000C DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 Table 14. Flash data register 1 low Bit Data Input 15:0 DIN(15:0) These bits must be written with ...

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Internal Flash memory 4.4.10 Flash address register high FARH (0x0E 0012 Table 17. Flash address register high Bit Address 20:16 ADD(20:16) These bits must be written with the address of the Flash location to program in the ...

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ST10F276Z5 Table 18. Flash error register (continued) Bit Sequence error This bit is automatically set when the control registers (FCR1H/L-FCR0H/L, FARH/L, SEQER FDR1H/L-FDR0H/L) are not correctly filled to execute a valid write operation. in this case no write operation is ...

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Internal Flash memory 4.5 Protection strategy The protection bits are stored in Non Volatile Flash cells inside XFLASH module, that are read once at reset and stored in 7 Volatile registers. Before they are read from the Non Volatile cells, ...

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ST10F276Z5 4.5.3 Flash non volatile write protection X register high FNVWPXRH (0x0E DF B2 Table 21. Flash non volatile write protection X register high Bit Write Protection Bank 3 / Sectors 1-0 (XFLASH) W3P(1:0) These bits, if ...

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... This bit, if erased at 1, allows to by-pass all the protections using the Debug features DBGP through the Test Interface. If programmed the contrary, all the debug features, the Test Interface and all the Flash Test modes are disabled. Even STMicroelectronics will not be able to access the device to run any eventual failure analysis. 4.5.7 ...

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ST10F276Z5 4.5.8 Flash non volatile access protection register 1 high FNVAPR1H (0x0E DFBE PEN15 PEN14 PEN13 PEN12 PEN11 PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0 Table 26. Flash non volatile ...

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Internal Flash memory Table 27. Summary of access protection level (continued) Fetching from XRAM Fetching from External Memory 4.5.10 Write protection The Flash modules have one level of Write Protections: each Sector of each Bank of each Flash Module can ...

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ST10F276Z5 4.6 Write operation examples In the following, examples for each kind of Flash write operation are presented. Word program Example: 32-bit Word Program of data 0xAAAAAAAA at address 0x0C5554 in XFLASH Module. FCR0H|= 0x2000; /*Set WPG in FCR0H*/ FARL ...

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Internal Flash memory Erase suspend, program and resume A Sector Erase operation can be suspended in order to program (Word or Double Word) another Sector. Example: Sector Erase of sector B3F1 of Bank 3 in XFLASH Module. FCR0H|= 0x0800;/*Set SER ...

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ST10F276Z5 Example 2: Enable Access and Debug Protection. FCR0H|= 0x0100;/*Set SPR in FCR0H*/ FARL = 0xDFB8;/*Load Add of register FNVAPR0 in FARL*/ FARH = 0x000E;/*Load Add of register FNVAPR0 in FARH*/ FDR0L = 0xFFFC;/*Load Data in FDR0L*/ FCR0H|= 0x8000;/*Operation start*/ ...

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Internal Flash memory Table 28. Flash write operations Operation Word Program (32-bit) Double Word Program (64-bit) Sector Erase Set Protection Program/Erase Suspend 46/239 Select bit Address and Data FARL/FARH WPG FDR0L/FDR0H FARL/FARH DWPG FDR0L/FDR0H FDR1L/FDR1H SER FCR1L/FCR1H SPR FDR0L/FDR0H SUSP ...

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ST10F276Z5 5 Bootstrap loader The ST10F276Z5 features innovative boot capabilities in order to support: ● User defined bootstrap (see Alternate bootstrap loader) ● Bootstrap via UART or bootstrap via CAN for the standard bootstrap 5.1 Selection among user-code, standard or ...

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Bootstrap loader Table 29. ST10F276Z5 boot mode selection P0.5 P0 5.2 Standard bootstrap loader The built-in bootstrap loader of the ST10F276Z5 provides a mechanism to load the startup program, which is executed ...

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ST10F276Z5 Valid dominant bit on CAN1 RxD The ST10F276Z5 starts bootstrapping via CAN1; the bootstrapping method is new and is described in the next paragraph 5.4. loader. It clearly illustrates how the new functionalities are implemented: ● UART: UART has ...

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Bootstrap loader Figure 5. ST10F276Z5 new standard bootstrap loader program flow START No Falling-edge on UART0 RxD? UART BOOT Start timer T6 No UART0 RxD = 1? Stop timer T6 Initialize UART Send acknowledge Address = FA40h No Byte received? ...

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ST10F276Z5 5.2.3 Booting steps As Figure 6 shows, booting the device with the boot loader code occurs in a minimum of four steps: 1. The device is reset with P0L.4 low. 2. The internal new bootstrap code runs on the ...

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Bootstrap loader Figure 7. Hardware provisions to activate the BSL P0L.4 5.2.5 Memory configuration in bootstrap loader mode The configuration (that is, the accessibility) of the device memory areas after reset in Bootstrap Loader mode differs from the standard case. ...

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ST10F276Z5 Figure 8. Memory configuration after reset BSL mode active EA pin Code fetch from internal FLASH area Data fetch from internal FLASH area 1. As long as the device is in BSL, the user’s software should not try to ...

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Bootstrap loader 5.2.7 Exiting bootstrap loader mode To execute a program in normal mode, the BSL mode must first be exits BSL mode at a software reset (level on P0L.4 is ignored hardware reset (P0L.4 must be high ...

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ST10F276Z5 Figure 9. UART bootstrap loader sequence RSTIN P0L.4 RxD0 TxD0 CSP:IP 1. BSL initialization time, > 1ms @ fCPU = 40 MHz. 2. Zero byte (1 start bit, eight ‘0’ data bits, 1 stop bit), sent by host. 3. ...

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Bootstrap loader 5.3.3 ST10 Configuration in UART BSL (RS232 or K-Line) When the ST10F276Z5 enters BSL mode on UART, the configuration shown in automatically set (values that deviate from the normal reset values are marked in bold). Table 31. ST10 ...

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ST10F276Z5 This process may go through several iterations or may directly execute the final application. In all cases the device still runs in BSL mode, that is, with the watchdog timer disabled and limited access to the internal Flash area. ...

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Bootstrap loader standard baud rate in this case would be 1200 baud. Baud rates below overflow. In this case, ASC0 cannot be initialized properly. The maximum baud rate (B still does not exceed the limit, that is, ...

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ST10F276Z5 The Bootstrap Loader can load ● the complete application software into ROM-less systems, ● temporary software into complete systems for testing or calibration, ● a programming routine for Flash devices. The BSL mechanism may be used for standard system ...

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Bootstrap loader 5.4.3 ST10 configuration in CAN BSL When the ST10F276Z5 enters BSL mode via CAN, the configuration shown in automatically set (values that deviate from the normal reset values are marked in bold). Table 32. ST10 configuration in CAN ...

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ST10F276Z5 mode. Most probably the initially loaded routine will load additional code or data average application is likely to require substantially more than 64 instructions. This second receive loop may directly use the pre-initialized CAN interface to receive ...

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Bootstrap loader Error induced by the polling The code used for the polling is the following: WaitCom: JNB P4.5,CAN_Boot CAN JB P3.11,WaitCom BSET T6R .... CAN_Boot: BSET PWMCON0.0 JMPR cc_UC,WaitRecessiveBit WaitDominantBit: JB P4.5,WaitDominantBit; wait for end of stuff bit WaitRecessiveBit: ...

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ST10F276Z5 Table 33. BRP and PT0 values BRP The error coming from the measurement of the 29 bit is maximal for the smallest BRP value and ...

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Bootstrap loader 5.4.6 Computing the baud rate error Considering the following conditions, a computation of the error is given as an example. ● CPU frequency: 20 MHz ● Target Bit Rate: 1 Mbit/s In these conditions, the content of PT0 ...

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ST10F276Z5 5.5 Comparing the old and the new bootstrap loader The following tables summarizes the differences between the old ST10 (boot via UART only) bootstrap and the new one (boot via UART or CAN). Table 34. Software topics summary Old ...

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Bootstrap loader 5.5.2 Hardware aspects Although the new bootstrap loader is designed to be compatible with the old bootstrap loader, there are a few hardware requirements for the new bootstrap loader as summarized in Table 35. Table 35. Hardware topics ...

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ST10F276Z5 5.6.4 ST10 configuration in alternate boot mode When the ST10F276Z5 enters BSL mode via CAN, the configuration shown in automatically set (values that deviate from the normal reset values are marked in bold). Table 36. ST10 configuration in alternate ...

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Bootstrap loader 5.6.6 Exiting alternate boot mode Once the ABM mode is entered, it can be exited only with a software or hardware reset. Note: See note from Section 5.2.7 5.6.7 Alternate boot user software If the rules described previously ...

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ST10F276Z5 5.6.10 EMUCON register EMUCON (FE0Ah / 05h Table 37. ABM bit description Bit ABM Flag (or TMOD3) ‘0’: Alternate Boot mode is not selected by reset configuration on P0L[5..4] ABM ‘1’: Alternate Boot mode is selected ...

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Bootstrap loader 5.7 Selective boot mode The selective boot is a subcase of the Alternate Boot mode. When none of the signatures are correct, instead of executing the standard bootstrap loader (triggered by P0L.4 low at reset), an additional check ...

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ST10F276Z5 Figure 13. Reset boot sequence Software checks user reset vector (K1 is OK?) Software Checks alternate reset vector (K2 is OK?) Long jump to ABM / User Flash Start at 09’0000h RSTIN Yes (P0L[5..4] = ‘01’) ...

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Central processing unit (CPU) 6 Central processing unit (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask ...

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ST10F276Z5 6.1 Multiplier-accumulator unit (MAC) The MAC coprocessor is a specialized coprocessor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms. The standard ST10 CPU has been modified to ...

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Central processing unit (CPU) 6.2 Instruction set summary The Table 39 lists the instructions of the ST10F276Z5. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Table 39. Standard instruction set summary Mnemonic ADD(B) ...

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ST10F276Z5 Table 39. Standard instruction set summary (continued) Mnemonic J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Jump relative if ...

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Central processing unit (CPU) 6.3 MAC coprocessor specific instructions The Table 40 lists the MAC instructions of the ST10F276Z5. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Note that all MAC instructions are ...

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ST10F276Z5 7 External bus controller All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required one of four different ...

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Interrupt system 8 Interrupt system The interrupt response time for internal program execution is from 78 to 187 MHz CPU clock. The ST10F276Z5 architecture supports several mechanisms for fast and flexible response to service requests that can ...

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ST10F276Z5 Table 41. Interrupt sources (continued) Source of Interrupt or PEC Service Request CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 ...

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Interrupt system Table 41. Interrupt sources (continued) Source of Interrupt or PEC Service Request GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC ...

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ST10F276Z5 available vector. If more than one source is enabled to issue the request, the service routine will have to take care to identify the real event to be serviced. This can easily be done by checking the flag bits ...

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Interrupt system Table 42. X-Interrupt detailed mapping (continued) ASC1 Error PLL Unlock / OWD PWM1 Channel 3...0 8.2 Exception and error traps list Table 43 shows all of the possible exceptions or error conditions that can arise during run- time. ...

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ST10F276Z5 9 Capture / compare (CAPCOM) units The ST10F276Z5 has two 16-channel CAPCOM units which support generation and control of timing sequences channels with a maximum resolution of 125 MHz CPU clock. The ...

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Capture / compare (CAPCOM) units Table 44. Compare modes (continued) Compare modes Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer Mode 3 period is generated Double Register Two registers operate ...

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ST10F276Z5 10 General purpose timer unit The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The ...

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General purpose timer unit Table 48. GPT1 timer input frequencies, resolutions and periods at 64 MHz MHz CPU 000b Pre-scaler factor 8 Input Freq 8 MHz Resolution 125 ns Period maximum 8.2 ms 16.4 ms Figure 17. ...

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ST10F276Z5 10.2 GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock ...

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General purpose timer unit Figure 18. Block diagram of GPT2 T5EUD CPU Clock T5IN CAPIN T6IN CPU Clock T6EUD 88/239 T5 2n n=2...9 GPT2 Timer T5 Mode Control Clear Capture GPT2 CAPREL T6 GPT2 Timer T6 Mode 2n n=2...9 Control ...

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ST10F276Z5 11 PWM modules Two pulse width modulation modules are available on ST10F276Z5: standard PWM0 and XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned or centre-aligned PWM. In addition, the PWM modules can generate ...

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PWM modules Table 52. PWM unit frequencies and resolutions at 64 MHz CPU clock Mode Resolution Mode 0 CPU Clock/1 15.6 ns CPU Clock/64 Mode 1 CPU Clock/1 15.6 ns CPU Clock/64 90/239 8-bit 10-bit 250 kHz 62.5 kHz 1.0µs ...

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ST10F276Z5 12 Parallel ports 12.1 Introduction The ST10F276Z5 MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications. The ST10F276Z5 has nine groups of I/O lines ...

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Parallel ports 12.2 I/Os special features 12.2.1 Open drain mode Some of the I/O ports of ST10F276Z5 support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to get an AND wired ...

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ST10F276Z5 ‘1’, because its output is ANDed with the alternate output data (except for PWM output signals). If the alternate input function of a pin is used, the direction of the pin must be programmed for input (DPx.y=‘0’ ...

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A/D converter 13 A/D converter A 10-bit A/D converter with 16+8 multiplexed input channels and a sample and hold circuit is integrated on-chip. An automatic self-calibration adjusts the A/D converter module to process parameter variations at each reset event. The ...

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ST10F276Z5 register. The data can be transferred to the RAM by interrupt software management or using the PEC data transfer. ● Wait for ADDAT read mode: When using continuous modes, in order to avoid to overwrite the result of the ...

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Serial channels 14 Serial channels Serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided four serial interfaces: two asynchronous / synchronous serial channels (ASC0 and ASC1) and two high-speed synchronous serial channel (SSC0 ...

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ST10F276Z5 Table 54. ASC asynchronous baud rates by reload value and deviation errors (f S0BRS = ‘0’, f CPU Baud rate (Baud) Deviation error 2 000 000 0.0% / 0.0% 112 000 +1.5% / -7.0% 56 000 +1.5% / -3.0% ...

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Serial channels Table 55. ASC synchronous baud rates by reload value and deviation errors (f S0BRS = ‘0’, f CPU Baud rate (Baud) Deviation error 900 0.0% / 0.0% 612 0.0% / 0.0% Table 56. ASC synchronous baud rates by ...

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ST10F276Z5 Table 57. Synchronous baud rate and reload values (f Baud rate Reserved Can be used only with f lower) 6.6M Baud 5M Baud 2.5M Baud 1M Baud 100K Baud 10K Baud 1K Baud 306 Baud Table 58. Synchronous baud ...

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I C interface interface 2 The integrated I C Bus Module handles the transmission and reception of frames over the two-line SDA/SCL in accordance with the I operate in slave mode, in master mode or ...

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ST10F276Z5 16 CAN modules The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active based on the C-CAN ...

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CAN modules 16.2 CAN bus configurations Depending on application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F276Z5 is able to support these ...

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ST10F276Z5 Multiple CAN bus The ST10F276Z5 provides two CAN interfaces to support such kind of bus configuration as shown in Figure 22. Figure 22. Connection to two different CAN buses (e.g. for gateway application) CAN_H CAN_L Parallel mode In addition ...

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Real-time clock 17 Real-time clock The real-time clock is an independent timer, in which the clock is derived directly from the clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator) so that it can be ...

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ST10F276Z5 18 Watchdog timer The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in ...

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System reset 19 System reset System reset initializes the MCU in a predefined state. There are six ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 61. Reset event definition ...

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ST10F276Z5 19.2 Asynchronous reset An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level. Then the device is immediately (after the input filter delay) forced in reset default state. It pulls low ...

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System reset In next Figure 24 respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded FLASH module when selected. Note: Never power the device without keeping RSTIN pin grounded: the device could ...

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ST10F276Z5 Figure 24. Asynchronous power-on RESET ( XTAL1 RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST ≤ 1.2 ms (for resonator oscillation + PLL stabilization) ≤ 10.2 ms (for crystal ...

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System reset Figure 25. Asynchronous power-on RESET ( XTAL1 RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST TCL depending on clock source selection. Hardware reset The asynchronous ...

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ST10F276Z5 Figure 26. Asynchronous hardware RESET ( RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (internal) FLARST RST This timing can be longer than Port0 settling time + PLL synchronization (if needed, that is 1. P0(15:13) changed). ...

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System reset Figure 27. Asynchronous hardware RESET ( RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST This timing can be longer than Port0 settling time + PLL synchronization (if needed, that is 1. P0(15:13) changed). It ...

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ST10F276Z5 19.3 Synchronous reset (warm reset) A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high level. In order to properly activate the internal reset logic of the device, the RSTIN pin must ...

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System reset always with FFFFh, which leads to an illegal opcode and consequently a trap event is generated. Exit from synchronous reset state The reset sequence is extended until RSTIN level becomes high. Besides internally prolonged by the ...

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ST10F276Z5 Figure 28. Synchronous short / long hardware RESET ( ≤4 TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT RPD 1. RSTIN assertion can be released there. ...

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System reset Figure 29. Synchronous short / long hardware RESET ( RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST RSTOUT RPD 1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum ...

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ST10F276Z5 Figure 30. Synchronous long hardware RESET ( RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT RPD 1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (around 2.5 ...

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System reset Figure 31. Synchronous long hardware RESET ( TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST RSTOUT RPD 1. If during the reset condition (RSTIN low), RPD voltage ...

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ST10F276Z5 19.4 Software reset A software reset sequence can be triggered at any time by the protected SRST (software reset) instruction. This instruction can be deliberately executed within a program, e.g. to leave bootstrap loader mode hardware ...

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System reset Figure 32 WDT unidirectional RESET ( RSTIN P0[15:13] P0[12:8] P0[7:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT Figure 33 WDT unidirectional RESET ( RSTIN P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT ...

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ST10F276Z5 19.6 Bidirectional reset As shown in the previous sections, the RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). RSTOUT pin stays active low beyond the end ...

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System reset internal signal RSTF) is sufficiently held low by the external hardware to inject a Long Hardware reset. After this occurrence, the initialization routine is not able to recognize a Software or Watchdog bidirectional reset event, since a different ...

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ST10F276Z5 Figure 35 WDT bidirectional RESET ( RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT ≥ ≤ 500 ns not transparent not t. transparent not ...

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System reset Figure 36 WDT bidirectional RESET (EA=0) followed RESET RSTIN RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT 19.7 Reset circuitry Internal reset circuitry is described in resistor of 50kΩ to 250kΩ ...

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ST10F276Z5 To ensure correct power-up reset with controlled supply current consumption, specially if clock signal requires a long period of time to stabilize, an asynchronous hardware reset is required during power-up. For this reason recommended to connect the ...

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System reset Figure 38. System reset circuit ST10F276Z5 Figure 39. Internal (simplified) reset circuitry Internal Reset Signal 126/239 External Hardware RSTIN o.d. R0 Open Drain Inverter RPD + C0 EINIT Instruction Clr Q Set ...

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ST10F276Z5 19.8 Reset application examples Next two timing diagrams bidirectional internal reset events (Software and Watchdog) including in particular the external capacitances charge and discharge transients (refer also to external circuit scheme). Figure 40. Example of software or watchdog bidirectional ...

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System reset Figure 41. Example of software or watchdog bidirectional reset ( 128/239 ST10F276Z5 ...

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ST10F276Z5 19.9 Reset summary A summary of the different reset events is reported in the table below. Table 62. Reset event Event Asynch. Power-on Reset Asynch ...

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System reset Table 62. Reset event (continued) Event Synch Synch. (2) Software Reset Synch Synch Synch Synch. (2) Watchdog Reset 0 1 ...

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ST10F276Z5 Figure 42. PORT0 bits latched into the different registers after reset H.7 H.6 CLKCFG RP0H CLKCFG Clock Generator P0L.7 ROMEN 10 9 PORT0 H.5 H.4 H.3 H.2 H.1 H.0 L.7 SALSEL CSSEL WRC BUSTYP CSSEL WRC SALSEL Port 4 ...

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Power reduction modes 20 Power reduction modes Three different power reduction modes with different levels of power reduction have been implemented in the ST10F276Z5. In Idle mode only CPU is stopped, while peripheral still operate. In Power-down mode both CPU ...

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ST10F276Z5 Before entering Power-down mode (by executing the instruction PWRDN), bit VREGOFF in XMISC register must be set. Note: Leaving the main voltage regulator active during Power-down may lead to unexpected behavior (ex: CPU wake-up) and power consumption higher than ...

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Power reduction modes In normal running mode (that is when main V during reset to exercise the EA functionality associated with the same pin: the voltage supply for the circuitries which are usually biased with V oscillator used in conjunction ...

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ST10F276Z5 Warning: 20.3.2 Exiting Standby mode After the system has entered the Standby mode, the procedure to exit this mode consists of a standard Power-on sequence, with the only difference that the RAM is already powered through V internal reference ...

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Power reduction modes 20.3.4 Power reduction modes summary In the following Table 64: Power reduction modes Power reduction modes is reported. Table 64. Power reduction modes summary Mode Idle Power-down Standby 136/239 on on off off on ...

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ST10F276Z5 21 Programmable output clock divider A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range. When CLKOUT function is enabled by setting ...

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Register set 22 Register set This section summarizes all registers implemented in the ST10F276Z5, and explains the description format used in the chapters to describe the function and layout of the SFRs. For easy reference, the registers (except for GPRs) ...

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ST10F276Z5 22.2 General purpose registers (GPRs) The GPRs form the register bank that the CPU works with. This register bank may be located anywhere within the internal RAM via the Context Pointer (CP). Due to the addressing mechanism, GPR banks ...

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Register set Table 67. General purpose registers (GPRs) bytewise addressing (continued) Name RL0 (CP RL3 (CP RH3 (CP RL4 (CP RH4 (CP RL5 (CP RH5 (CP ...

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ST10F276Z5 22.3 Special function registers ordered by name The following table lists in alphabetical order all SFRs which are implemented in the ST10F276Z5. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) ...

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Register set Table 68. Special function registers ordered by address (continued) Physical Name address CC12 FE98h CC12IC b FF90h CC13 FE9Ah CC13IC b FF92h CC14 FE9Ch CC14IC b FF94h CC15 FE9Eh CC15IC b FF96h CC16 FE60h CC16IC b F160h E ...

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ST10F276Z5 Table 68. Special function registers ordered by address (continued) Physical Name address CC28 FE78h CC28IC b F178h E BCh CC29 FE7Ah CC29IC b F184h E C2h CC2IC b FF7Ch CC3 FE86h CC30 FE7Ch CC30IC b F18Ch E C6h CC31 ...

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Register set Table 68. Special function registers ordered by address (continued) Physical Name address DP0H b F102h E 81h DP0L b F100h E 80h DP1H b F106h E 83h DP1L b F104h E 82h DP2 b FFC2h DP3 b FFC6h ...

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ST10F276Z5 Table 68. Special function registers ordered by address (continued) Physical Name address ODP6 b F1CEh E E7h ODP7 b F1D2h E E9h ODP8 b F1D6h E EBh ONES b FF1Eh P0H b FF02h P0L b FF00h P1H b FF06h ...

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Register set Table 68. Special function registers ordered by address (continued) Physical Name address PW0 FE30h PW1 FE32h PW2 FE34h PW3 FE36h PWMCON0 b FF30h PWMCON1 b FF32h PWMIC b F17Eh E BFh QR0 F004h E 02h QR1 F006h E ...

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ST10F276Z5 Table 68. Special function registers ordered by address (continued) Physical Name address T0IC b FF9Ch T0REL FE54h T1 FE52h T1IC b FF9Eh T1REL FE56h T2 FE40h T2CON b FF40h T2IC b FF60h T3 FE42h T3CON b FF42h T3IC b ...

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Register set Table 68. Special function registers ordered by address (continued) Physical Name address XP3IC b F19Eh E CFh XPERCON F024h E 12h ZEROS b FF1Ch 22.4 Special function registers ordered by address The following table lists by order of ...

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ST10F276Z5 Table 69. Special function registers ordered by address (continued) Physical Name address IDMANUF F07Eh E ADDAT2 F0A0h E SSCTB F0B0h E SSCRB F0B2h E SSCBR F0B4h E DP0L b F100h E DP0H b F102h E DP1L b F104h E ...

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Register set Table 69. Special function registers ordered by address (continued) Physical Name address XP3IC b F19Eh E EXICON b F1C0h E ODP2 b F1C2h E PICON b F1C4h E ODP3 b F1C6h E ODP4 b F1CAh E ODP6 b ...

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ST10F276Z5 Table 69. Special function registers ordered by address (continued) Physical Name address T6 FE48h CAPREL FE4Ah T0 FE50h T1 FE52h T0REL FE54h T1REL FE56h MAL FE5Ch MAH FE5Eh CC16 FE60h CC17 FE62h CC18 FE64h CC19 FE66h CC20 FE68h CC21 ...

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Register set Table 69. Special function registers ordered by address (continued) Physical Name address CC10 FE94h CC11 FE96h CC12 FE98h CC13 FE9Ah CC14 FE9Ch CC15 FE9Eh ADDAT FEA0h WDT FEAEh S0TBUF FEB0h S0RBUF FEB2h S0BG FEB4h PECC0 FEC0h PECC1 FEC2h ...

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ST10F276Z5 Table 69. Special function registers ordered by address (continued) Physical Name address ZEROS b FF1Ch ONES b FF1Eh T78CON b FF20h CCM4 b FF22h CCM5 b FF24h CCM6 b FF26h CCM7 b FF28h PWMCON0 b FF30h PWMCON1 b FF32h ...

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Register set Table 69. Special function registers ordered by address (continued) Physical Name address CC3IC b FF7Eh CC4IC b FF80h CC5IC b FF82h CC6IC b FF84h CC7IC b FF86h CC8IC b FF88h CC9IC b FF8Ah CC10IC b FF8Ch CC11IC b ...

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ST10F276Z5 Table 69. Special function registers ordered by address (continued) Physical Name address DP7 b FFD2h P8 b FFD4h DP8 b FFD6h MRW b FFDAh MCW b FFDCh MSW b FFDEh 22.5 X-registers sorted by name The following table lists ...

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Register set Table 70. X-Registers ordered by name (continued) Name CAN1IF2DA1 CAN1IF2DA2 CAN1IF2DB1 CAN1IF2DB2 CAN1IF2M1 CAN1IF2M2 CAN1IF2MC CAN1IP1 CAN1IP2 CAN1IR CAN1MV1 CAN1MV2 CAN1ND1 CAN1ND2 CAN1SR CAN1TR CAN1TR1 CAN1TR2 CAN2BRPER CAN2BTR CAN2CR CAN2EC CAN2IF1A1 CAN2IF1A2 CAN2IF1CM CAN2IF1CR CAN2IF1DA1 CAN2IF1DA2 CAN2IF1DB1 CAN2IF1DB2 ...

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ST10F276Z5 Table 70. X-Registers ordered by name (continued) Name CAN2IF2A2 CAN2IF2CM CAN2IF2CR CAN2IF2DA1 CAN2IF2DA2 CAN2IF2DB1 CAN2IF2DB2 CAN2IF2M1 CAN2IF2M2 CAN2IF2MC CAN2IP1 CAN2IP2 CAN2IR CAN2MV1 CAN2MV2 CAN2ND1 CAN2ND2 CAN2SR CAN2TR CAN2TR1 CAN2TR2 I2CCCR1 I2CCCR2 I2CCR I2CDR I2COAR1 I2COAR2 I2CSR1 I2CSR2 RTCAH RTCAL ...

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Register set Table 70. X-Registers ordered by name (continued) Name RTCH RTCL RTCPH RTCPL XCLKOUTDIV XEMU0 XEMU1 XEMU2 XEMU3 XIR0CLR XIR0SEL XIR0SET XIR1CLR XIR1SEL XIR1SET XIR2CLR XIR2SEL XIR2SET XIR3CLR XIR3SEL XIR3SET XMISC XP1DIDIS XPEREMU XPICON XPOLAR XPP0 XPP1 XPP2 XPP3 ...

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ST10F276Z5 Table 70. X-Registers ordered by name (continued) Name XPT2 XPT3 XPW0 XPW1 XPW2 XPW3 XPWMCON0 XPWMCON0CLR XPWMCON0SET XPWMCON1 XPWMCON1CLR XPWMCON1SET XPWMPORT XS1BG XS1CON XS1CONCLR XS1CONSET XS1PORT XS1RBUF XS1TBUF XSSCBR XSSCCON XSSCCONCLR XSSCCONSET XSSCPORT XSSCRB XSSCTB Physical Description address EC14h ...

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Register set 22.6 X-registers ordered by address The following table lists by order of their physical addresses all X-Bus registers which are implemented in the ST10F276Z5. Although also physically mapped on X-Bus memory space, the Flash control registers are listed ...

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ST10F276Z5 Table 71. X-registers ordered by address (continued) Name XPICON XIR2SEL XIR2SET XIR2CLR XP1DIDIS XIR3SEL XIR3SET XIR3CLR XMISC XEMU0 XEMU1 XEMU2 XEMU3 XPEREMU XPWMCON0 XPWMCON1 XPOLAR XPWMCON0SET XPWMCON0CLR XPWMCON1SET XPWMCON1CLR XPT0 XPT1 XPT2 XPT3 XPP0 XPP1 XPP2 XPP3 XPW0 Physical ...

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Register set Table 71. X-registers ordered by address (continued) Name XPW1 XPW2 XPW3 XPWMPORT RTCCON RTCPL RTCPH RTCDL RTCDH RTCL RTCH RTCAL RTCAH CAN2CR CAN2SR CAN2EC CAN2BTR CAN2IR CAN2TR CAN2BRPER CAN2IF1CR CAN2IF1CM CAN2IF1M1 CAN2IF1M2 CAN2IF1A1 CAN2IF1A2 CAN2IF1MC CAN2IF1DA1 CAN2IF1DA2 CAN2IF1DB1 ...

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ST10F276Z5 Table 71. X-registers ordered by address (continued) Name CAN2IF2M2 CAN2IF2A1 CAN2IF2A2 CAN2IF2MC CAN2IF2DA1 CAN2IF2DA2 CAN2IF2DB1 CAN2IF2DB2 CAN2TR1 CAN2TR2 CAN2ND1 CAN2ND2 CAN2IP1 CAN2IP2 CAN2MV1 CAN2MV2 CAN1CR CAN1SR CAN1EC CAN1BTR CAN1IR CAN1TR CAN1BRPER CAN1IF1CR CAN1IF1CM CAN1IF1M1 CAN1IF1M2 CAN1IF1A1 CAN1IF1A2 CAN1IF1MC CAN1IF1DA1 ...

Page 164

Register set Table 71. X-registers ordered by address (continued) Name CAN1IF2CR CAN1IF2CM CAN1IF2M1 CAN1IF2M2 CAN1IF2A1 CAN1IF2A2 CAN1IF2MC CAN1IF2DA1 CAN1IF2DA2 CAN1IF2DB1 CAN1IF2DB2 CAN1TR1 CAN1TR2 CAN1ND1 CAN1ND2 CAN1IP1 CAN1IP2 CAN1MV1 CAN1MV2 164/239 Physical Description address EF40h CAN1: IF2 command request EF42h CAN1: ...

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ST10F276Z5 22.7 Flash registers ordered by name The following table lists by order of their names all FLASH control registers which are implemented in the ST10F276Z5. Note that as they are physically mapped on the X-Bus, these registers are not ...

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Register set 22.8 Flash registers ordered by address The following table lists by order of their physical addresses all FLASH control registers which are implemented in the ST10F276Z5. Note that as they are physically mapped on the X-Bus, these registers ...

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... The internal Flash and size identifier ● the programming voltage description IDMANUF (F07Eh / 3Fh Table 74. MANUF description Bit Manufacturer identifier MANUF 020h: STMicroelectronics manufacturer (JTAG worldwide normalization) IDCHIP (F07Ch / 3Eh Table 75. IDCHIP description Bit Device identifier IDCHIP 114h: ST10F276Z5 Identifier (276) Device revision identifier ...

Page 168

Register set Table 76. IDMEM description Bit Internal memory size MEMSIZE Internal Memory size (MEMSIZE) (in Kbyte) 0D0h for ST10F276Z5 (832 Kbytes) Internal memory type ‘0h’: ROM-Less ‘1h’: (M) ROM memory MEMTYP ‘2h’: (S) Standard FLASH memory ...

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ST10F276Z5 22.10 System configuration registers The ST10F276Z5 registers are used for a different configuration of the overall system. These registers are described below. SYSCON (FF12h / 89h ROM STKSZ Note: SYSCON Reset Value ...

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Register set Table 79. SYSCON description (continued) Bit Write configuration control (inverted copy of WRC bit of RP0H) WRCFG ‘0’: Pins WR and BHE retain their normal function. ‘1’: Pin WR acts as WRL, pin BHE acts as WRH. System ...

Page 171

ST10F276Z5 BUSCON4 (FF1Ah / 8Dh CSWEN4 CSREN4 RDYPOL4 RDYEN4 RW RW Table 80. BUSCON4 description Bit Memory cycle time control (number of memory cycle time wait-states) ’0000’: 15 wait-states (Number of wait-states = 15 - [MCTC]). MCTC ...

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Register set Note: BUSCON0 is initialized with 0000h pin is high during reset pin is low during reset, bit BUSACT0 and ALECTRL0 are set to ‘1’ and bit field BTYP is loaded with the bus configuration ...

Page 173

ST10F276Z5 Table 82. EXIxES bit description Bit 00 = Fast external interrupts disabled: Standard mode. EXxIN pin not taken in account for entering/exiting Power-down mode Interrupt on positive edge (rising). Enter Power-down mode if EXiIN = ‘0’, exit ...

Page 174

Register set Table 85. SFR area description Bit Group level Defines the internal order for simultaneous requests of the same priority. GLVL ’3’: Highest group priority ’0’: Lowest group priority Interrupt priority level Defines the priority level for the arbitration ...

Page 175

ST10F276Z5 Table 86. ESFR description (continued) Bit RTC enable ‘0’: Accesses to the on-chip RTC module are disabled, external access performed. Address range 00’ED00h-00’EDFF is directed to external memory only if XRTCEN CAN1EN, CAN2EN, XASCEN, XSSCEN, XI2CEN, XPWMEN and XMISCEN ...

Page 176

Register set The default XPER selection after Reset is such that CAN1 is enabled, CAN2 is disabled, XRAM1 (2 Kbyte XRAM) is enabled and XRAM2 (64 Kbyte XRAM) is disabled; all the other X-Peripherals are disabled after Reset. Register XPERCON ...

Page 177

ST10F276Z5 22.11 Emulation dedicated registers Four additional registers are implemented for emulation purposes only. Similarly to XPEREMU, they are write-only registers. XEMU0 (EB76h XEMU1 (EB78h XEMU2 (EB7Ah XEMU3 (EB7Ch ...

Page 178

Electrical characteristics 23 Electrical characteristics 23.1 Absolute maximum ratings Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any ...

Page 179

ST10F276Z5 23.3 Power considerations The average chip-junction temperature, T following equation: Where: is the Ambient Temperature in ° Θ is the Package Junction-to-Ambient Thermal Resistance, in °C/ the sum the ...

Page 180

Electrical characteristics Table 91. Package characteristics Package Die PQFP 144 LQFP 144 LQFP 144 23.4 Parameter interpretation The parameters listed in the following tables represent the characteristics of the ST10F276Z5 and its demands on the system. Where the ST10F276Z5 logic ...

Page 181

ST10F276Z5 Table 92. DC characteristics (continued) Symbol Input high voltage (TTL mode (except RSTIN, EA, NMI, RPD, IH XTAL1) Input high voltage (CMOS mode (except RSTIN, EA, NMI, RPD, IHS XTAL1) Input high voltage RSTIN, EA, ...

Page 182

Electrical characteristics Table 92. DC characteristics (continued) Symbol | | I CC Input leakage current (P5[15:0]) OZ1 Input leakage current | | I CC OZ2 (all except P5[15:0], P2.0, RPD Input leakage current (P2.0) OZ3 | ...

Page 183

ST10F276Z5 Table 92. DC characteristics (continued) Symbol Standby supply current I (RTC on, 32 kHz Oscillator on, SB2 main VDD off, VSTBY on) Standby supply current I SB3 (VDD transient condition) 1. This specification is not valid for outputs which ...

Page 184

Electrical characteristics Figure 44. Port2 test mode structure Figure 45. Supply current versus the operating frequency (RUN and IDLE modes) 150 100 184/239 Clock Input Alternate Data Input Latch Fast External Interrupt Input Test Mode Flash Sense ...

Page 185

ST10F276Z5 23.6 Flash characteristics = 5 V ± 10 Table 93. Flash characteristics Parameter Word program (32-bit) Double word program (2) (64-bit) Bank 0 program (384K) (double word program) Bank 1 program (128K) (double word program) Bank ...

Page 186

... EEPROM Program/Erase cycles. For an efficient use of the Read While Write feature and/or EEPROM Emulation please refer to dedicated Application Note document (AN2061 - EEPROM Emulation with ST10F2xx). Contact your local field service, local sales person or STMicroelectronics representative to obtain a copy of such a guideline document. 186/239 ...

Page 187

ST10F276Z5 23.7 A/D converter characteristics = 5 V ± 10 ≤ V ≤ AGND Table 95. A/D converter characteristics Symbol V SR Analog reference voltage AREF V SR Analog ground voltage AGND V SR ...

Page 188

Electrical characteristics 6. DNL, INL, OFS and TUE are tested at V design characterization for all other voltages within the defined voltage range. "LSB" has a value of V For Port5 channels, the specified TUE (± 2LSB) is also guaranteed ...

Page 189

ST10F276Z5 Table 96. A/D Converter programming (continued) ADCTC ADSTC Note: The total conversion time is compatible with the formula valid ...

Page 190

Electrical characteristics Nonlinearity error Nonlinearity error is the deviation between actual and the best-fitting A/D conversion charac- teristics (see Figure – Differential nonlinearity error is the actual step dimension versus the ideal one (1 LSB IDEAL – Integral nonlinearity error ...

Page 191

ST10F276Z5 23.7.4 Analog reference pins The accuracy of the A/D converter depends on the accuracy of its analog reference: A noise in the reference results in proportionate error in a conversion. A low pass filter on the A/D converter reference ...

Page 192

Electrical characteristics Input leakage and external circuit The series resistor utilized to limit the current to a pin (see R with a large source impedance, can lead to a degradation of A/D converter accuracy when input leakage is present. Data ...

Page 193

ST10F276Z5 In particular two different transient periods can be distinguished (see 1. A first and quick charge transfer from the internal capacitances C sampling capacitance C Considering a worst case (since the time constant in reality would be faster) in ...

Page 194

Electrical characteristics selected (fastest conversion rate at a specific channel): In conclusion evident that the time constant of the filter R charge level on C the sampling switch is closed. Figure 49. Anti-aliasing filter and conversion rate Analog ...

Page 195

ST10F276Z5 23.7.6 Example of external network sizing The following hypothesis is formulated in order to proceed with designing the external net- work on A/D converter input pins: ● Analog signal source bandwidth (f ● Conversion rate (f ● Sampling time ...

Page 196

Electrical characteristics then half a count (considering the worst case when V The other conditions to verify are if the time constants of the transients are really and significantly shorter than the sampling period duration T For a complete set ...

Page 197

ST10F276Z5 23.8.2 Definition of internal timing The internal operation of the ST10F276Z5 is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. The specification ...

Page 198

Electrical characteristics 23.8.3 Clock generation modes The following table associates the combinations of these 3 bits with the respective clock generation mode. Table 97. On-chip clock generator selections P0.15-13 CPU frequency (P0H.7-5) f CPU XTAL 1 ...

Page 199

ST10F276Z5 Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value can be calculated by the following formula: For two consecutive TCLs, the deviation caused by the duty cycle the duration of ...

Page 200

Electrical characteristics Due to this adaptation to the input clock, the frequency of f locked The slight variation causes a jitter of f XTAL individual TCLs. The timings listed in the AC Characteristics that refer to TCLs ...